Alex Forencich 5b14329483 axi: Clean up user signal width handling in AXI RAM IF modules ...

Signed-off-by: Alex Forencich <alex@alexforencich.com>

2026-03-20 00:06:23 -07:00

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lib

Reorganize repository

2025-05-18 12:25:59 -07:00

rtl

axi: Clean up user signal width handling in AXI RAM IF modules

2026-03-20 00:06:23 -07:00

tb

axi: Add AXI RAM interface and AXI dual port RAM

2026-03-19 18:12:37 -07:00