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mirror of https://github.com/fpganinja/taxi.git synced 2025-12-09 17:08:38 -08:00
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2abe774f8a01d269b9c082c506c4571633235e0c
taxi/tb
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Alex Forencich 2abe774f8a eth: Add 10G Ethernet MAC+PHY module with FIFOs and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2025-02-13 13:48:54 -08:00
..
axis
axis: Add AXI stream combination async FIFO/adapter module and testbench
2025-02-06 00:52:04 -08:00
eth
eth: Add 10G Ethernet MAC+PHY module with FIFOs and testbench
2025-02-13 13:48:54 -08:00
lfsr
lfsr: Add LFSR descrambler module and testbench
2025-02-05 15:29:12 -08:00
lss/taxi_uart
lss: Add UART module and testbench
2025-02-03 15:02:48 -08:00
ptp
ptp: Add PTP clock CDC module and testbench
2025-02-13 12:49:42 -08:00
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