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39 lines
1.3 KiB
Markdown
39 lines
1.3 KiB
Markdown
# Corundum for VCU108
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## Introduction
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This design targets the Xilinx VCU108 FPGA board.
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* USB UART
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* XFCP (921600 baud)
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* RJ-45 Ethernet port with Marvell 88E1111 PHY
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* Looped-back MAC via SGMII via Xilinx PCS/PMA core and LVDS IOSERDES
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* QSFP28
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* 10GBASE-R or 25GBASE-R MACs via GTY transceivers
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## Board details
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* FPGA: xcvu095-ffva2104-2-e
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* USB UART: Silicon Labs CP2105 SCI
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* PCIe: gen 3 x8 (~64 Gbps)
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* Reference oscillator: Fixed 156.25 MHz from Si570
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* 1000BASE-T PHY: Marvell 88E1111 via SGMII
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* 25GBASE-R PHY: Soft PCS with GTY transceivers
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## Licensing
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* Toolchain
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* Vivado Enterprise (requires license)
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* IP
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* No licensed vendor IP or 3rd party IP
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## How to build
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Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
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On the host system, run `make` in `modules/cndm` to build the driver. Ensure that the headers for the running kernel are installed, otherwise the driver cannot be compiled.
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## How to test
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Run `make program` to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod cndm.ko`. Check `dmesg` for output from driver initialization. Run `cndm_ddcmd.sh =p` to enable all debug messages.
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