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54 lines
747 B
Systemverilog
54 lines
747 B
Systemverilog
// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4 lite RAM testbench
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*/
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module test_taxi_axil_ram #
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(
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/* verilator lint_off WIDTHTRUNC */
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parameter DATA_W = 32,
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parameter ADDR_W = 16,
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parameter PIPELINE_OUTPUT = 0
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/* verilator lint_on WIDTHTRUNC */
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)
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();
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logic clk;
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logic rst;
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taxi_axil_if #(
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.DATA_W(DATA_W),
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.ADDR_W(ADDR_W+16)
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) s_axil(), m_axil();
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taxi_axil_ram #(
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.ADDR_W(ADDR_W),
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.PIPELINE_OUTPUT(PIPELINE_OUTPUT)
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)
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uut (
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.clk(clk),
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.rst(rst),
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/*
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* AXI4-Lite slave interface
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*/
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.s_axil_wr(s_axil),
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.s_axil_rd(s_axil)
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);
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endmodule
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`resetall
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