Alex Forencich 83c52e6744 axi: Add AXI-lite tie modules ...

Signed-off-by: Alex Forencich <alex@alexforencich.com>

2025-12-23 17:37:36 -08:00

..

apb

apb: Add APB width converter module and testbench

2025-11-12 23:05:12 -08:00

axi

axi: Add AXI-lite tie modules

2025-12-23 17:37:36 -08:00

axis

axis: Use bin2gray function in async FIFO

2025-11-12 17:05:38 -08:00

dma

dma: Cast RAM address width appropriately

2025-12-15 20:53:15 -08:00

eth

eth/example: Use logging.getLogger instead of SimLog

2025-11-17 21:34:06 -08:00

hip/rtl/us

eth: Add APB register interface to US/US+ transceiver wrappers

2025-11-13 14:15:20 -08:00

io/rtl

Clean up always blocks

2025-11-07 01:51:18 -08:00

lfsr

Use logic instead of reg

2025-11-07 02:14:19 -08:00

lss

Use logic instead of reg

2025-11-07 02:14:19 -08:00

math

math: Add MT19937 Mersenne Twister PRNG module and testbench

2025-10-15 22:14:21 -07:00

pcie

Use logic instead of reg

2025-11-07 02:14:19 -08:00

prim

Reorganize repository

2025-05-18 12:25:59 -07:00

ptp

Use logic instead of reg

2025-11-07 02:14:19 -08:00

stats

stats: Clean up casts

2025-09-07 14:58:16 -07:00

sync

Reorganize repository

2025-05-18 12:25:59 -07:00

xfcp

xfcp: Add taxi_xfcp_mod_apb.f

2025-11-13 12:08:40 -08:00

zircon

Clean up always blocks

2025-11-07 01:51:18 -08:00