taxi/example/KCU105/fpga

Taxi Example Design for KCU105

Introduction

This example design targets the Xilinx KCU105 FPGA board.

The design places looped-back MACs on the BASE-T port and SFP+ cages, as well as XFCP on the USB UART for monitoring and control.

• USB UART
  • XFCP (921600 baud)
• RJ-45 Ethernet port with Marvell 88E1111 PHY
  • Looped-back MAC via SGMII via Xilinx PCS/PMA core and LVDS IOSERDES
• SFP+ cages
  • Looped-back 1000BASE-X via Xilinx PCS/PMA core and GTH transceiver
  • Looped-back 10GBASE-R MAC via GTH transceiver

Board details

• FPGA: xcku040-ffva1156-2-e
• USB UART: Silicon Labs CP2105 SCI
• 1000BASE-T PHY: Marvell 88E1111 via SGMII
• 1000BASE-X PHY: Xilinx PCS/PMA core via GTH transceiver
• 10GBASE-R PHY: Soft PCS with GTH transceiver

Licensing

• Toolchain
  • Vivado Enterprise (requires license)
• IP
  • No licensed vendor IP or 3rd party IP

How to build

Run make in the appropriate fpga* subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.

How to test

Run make program to program the board with Vivado.

To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback. Do not connect the looped-back MAC to a network as the reflected packets may cause problems.