bslathi19/taxi
1
0
Fork 0
mirror of https://github.com/fpganinja/taxi.git synced 2025-12-07 16:28:40 -08:00
Code Issues Packages Projects Releases Wiki Activity

example: Enable statistics strings in example designs

Browse Source 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-04-17 00:34:53 -07:00
parent 0044782224
commit 6584ebb6cd
10 changed files with 63 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
example/Alveo/fpga/rtl/fpga_core.sv
View File

@@ -284,6 +284,9 @@ for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gty_clk
end
localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP1[4] = '{"QSFP1.1", "QSFP1.2", "QSFP1.3", "QSFP1.4"};
localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP2[4] = '{"QSFP2.1", "QSFP2.2", "QSFP2.3", "QSFP2.4"};
for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
localparam CLK = n;
@@ -314,7 +317,9 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
.STAT_TX_LEVEL(1),
.STAT_RX_LEVEL(1),
.STAT_ID_BASE(n*CNT*(16+16)),
.STAT_UPDATE_PERIOD(1024)
.STAT_UPDATE_PERIOD(1024),
.STAT_STR_EN(1),
.STAT_PREFIX_STR(n == 0 ? STAT_PREFIX_STR_QSFP1 : STAT_PREFIX_STR_QSFP2)
)
mac_inst (
.xcvr_ctrl_clk(clk_125mhz),

2
example/Arty/fpga/rtl/fpga_core.sv
View File

@@ -171,6 +171,8 @@ taxi_eth_mac_mii_fifo #(
.STAT_RX_LEVEL(1),
.STAT_ID_BASE(0),
.STAT_UPDATE_PERIOD(1024),
.STAT_STR_EN(1),
.STAT_PREFIX_STR("MII0"),
.TX_FIFO_DEPTH(16384),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(16384),

2
example/HTG940/fpga/rtl/fpga_core.sv
View File

@@ -162,6 +162,8 @@ taxi_eth_mac_1g_rgmii_fifo #(
.STAT_RX_LEVEL(1),
.STAT_ID_BASE(0),
.STAT_UPDATE_PERIOD(1024),
.STAT_STR_EN(1),
.STAT_PREFIX_STR("RGMII0"),
.TX_FIFO_DEPTH(16384),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(16384),

8
example/KC705/fpga/rtl/fpga_core.sv
View File

@@ -228,6 +228,8 @@ if (BASET_PHY_TYPE == "GMII") begin : baset_mac_gmii
.STAT_RX_LEVEL(1),
.STAT_ID_BASE(0),
.STAT_UPDATE_PERIOD(1024),
.STAT_STR_EN(1),
.STAT_PREFIX_STR("GMII0"),
.TX_FIFO_DEPTH(16384),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(16384),
@@ -316,6 +318,8 @@ end else if (BASET_PHY_TYPE == "RGMII") begin : baset_mac_rgmii
.STAT_RX_LEVEL(1),
.STAT_ID_BASE(0),
.STAT_UPDATE_PERIOD(1024),
.STAT_STR_EN(1),
.STAT_PREFIX_STR("RGMII0"),
.TX_FIFO_DEPTH(16384),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(16384),
@@ -399,6 +403,8 @@ end else if (BASET_PHY_TYPE == "SGMII") begin : baset_mac_sgmii
.STAT_RX_LEVEL(1),
.STAT_ID_BASE(0),
.STAT_UPDATE_PERIOD(1024),
.STAT_STR_EN(1),
.STAT_PREFIX_STR("SGMII0"),
.TX_FIFO_DEPTH(16384),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(16384),
@@ -496,6 +502,8 @@ taxi_eth_mac_1g_fifo #(
.STAT_RX_LEVEL(1),
.STAT_ID_BASE(16+16),
.STAT_UPDATE_PERIOD(1024),
.STAT_STR_EN(1),
.STAT_PREFIX_STR("SFP"),
.TX_FIFO_DEPTH(16384),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(16384),

11
example/KCU105/fpga/rtl/fpga_core.sv
View File

@@ -221,6 +221,8 @@ taxi_eth_mac_1g_fifo #(
.STAT_RX_LEVEL(1),
.STAT_ID_BASE(0),
.STAT_UPDATE_PERIOD(1024),
.STAT_STR_EN(1),
.STAT_PREFIX_STR("SGMII0"),
.TX_FIFO_DEPTH(16384),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(16384),
@@ -312,6 +314,8 @@ if (SFP_RATE == 0) begin : sfp_mac
.STAT_RX_LEVEL(1),
.STAT_ID_BASE((16+16)+(16+16)*0),
.STAT_UPDATE_PERIOD(1024),
.STAT_STR_EN(1),
.STAT_PREFIX_STR("SFP0"),
.TX_FIFO_DEPTH(16384),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(16384),
@@ -392,6 +396,8 @@ if (SFP_RATE == 0) begin : sfp_mac
.STAT_RX_LEVEL(1),
.STAT_ID_BASE((16+16)+(16+16)*1),
.STAT_UPDATE_PERIOD(1024),
.STAT_STR_EN(1),
.STAT_PREFIX_STR("SFP1"),
.TX_FIFO_DEPTH(16384),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(16384),
@@ -547,7 +553,10 @@ end else begin : sfp_mac
.STAT_TX_LEVEL(1),
.STAT_RX_LEVEL(1),
.STAT_ID_BASE(16+16),
.STAT_UPDATE_PERIOD(1024)
.STAT_UPDATE_PERIOD(1024)//,
// disabled due to verilator bug
// .STAT_STR_EN(1),
// .STAT_PREFIX_STR('{"SFP0", "SFP1"})
)
sfp_mac_inst (
.xcvr_ctrl_clk(clk),

6
example/VCU108/fpga/rtl/fpga_core.sv
View File

@@ -203,6 +203,8 @@ taxi_eth_mac_1g_fifo #(
.STAT_RX_LEVEL(1),
.STAT_ID_BASE(0),
.STAT_UPDATE_PERIOD(1024),
.STAT_STR_EN(1),
.STAT_PREFIX_STR("SGMII0"),
.TX_FIFO_DEPTH(16384),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(16384),
@@ -364,7 +366,9 @@ taxi_eth_mac_25g_us #(
.STAT_TX_LEVEL(1),
.STAT_RX_LEVEL(1),
.STAT_ID_BASE(16+16),
.STAT_UPDATE_PERIOD(1024)
.STAT_UPDATE_PERIOD(1024),
.STAT_STR_EN(1),
.STAT_PREFIX_STR('{"QSFP.1", "QSFP.2", "QSFP.3", "QSFP.4"})
)
qsfp_mac_inst (
.xcvr_ctrl_clk(clk),

9
example/VCU118/fpga/rtl/fpga_core.sv
View File

@@ -221,6 +221,8 @@ taxi_eth_mac_1g_fifo #(
.STAT_RX_LEVEL(1),
.STAT_ID_BASE(0),
.STAT_UPDATE_PERIOD(1024),
.STAT_STR_EN(1),
.STAT_PREFIX_STR("SGMII0"),
.TX_FIFO_DEPTH(16384),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(16384),
@@ -528,6 +530,9 @@ assign qsfp1_tx_n = qsfp_tx_n[3:0];
assign qsfp2_tx_p = qsfp_tx_p[7:4];
assign qsfp2_tx_n = qsfp_tx_n[7:4];
localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP1[4] = '{"QSFP1.1", "QSFP1.2", "QSFP1.3", "QSFP1.4"};
localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP2[4] = '{"QSFP2.1", "QSFP2.2", "QSFP2.3", "QSFP2.4"};
for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
localparam CNT = 4;
@@ -557,7 +562,9 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
.STAT_TX_LEVEL(1),
.STAT_RX_LEVEL(1),
.STAT_ID_BASE((16+16)+n*CNT*(16+16)),
.STAT_UPDATE_PERIOD(1024)
.STAT_UPDATE_PERIOD(1024),
.STAT_STR_EN(1),
.STAT_PREFIX_STR(n == 0 ? STAT_PREFIX_STR_QSFP1 : STAT_PREFIX_STR_QSFP2)
)
mac_inst (
.xcvr_ctrl_clk(clk_125mhz),

12
example/ZCU102/fpga/rtl/fpga_core.sv
View File

@@ -237,6 +237,8 @@ if (SFP_RATE == 0) begin : sfp_mac
.STAT_RX_LEVEL(1),
.STAT_ID_BASE((16+16)*0),
.STAT_UPDATE_PERIOD(1024),
.STAT_STR_EN(1),
.STAT_PREFIX_STR("SFP0"),
.TX_FIFO_DEPTH(16384),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(16384),
@@ -317,6 +319,8 @@ if (SFP_RATE == 0) begin : sfp_mac
.STAT_RX_LEVEL(1),
.STAT_ID_BASE((16+16)*1),
.STAT_UPDATE_PERIOD(1024),
.STAT_STR_EN(1),
.STAT_PREFIX_STR("SFP1"),
.TX_FIFO_DEPTH(16384),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(16384),
@@ -397,6 +401,8 @@ if (SFP_RATE == 0) begin : sfp_mac
.STAT_RX_LEVEL(1),
.STAT_ID_BASE((16+16)*2),
.STAT_UPDATE_PERIOD(1024),
.STAT_STR_EN(1),
.STAT_PREFIX_STR("SFP2"),
.TX_FIFO_DEPTH(16384),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(16384),
@@ -477,6 +483,8 @@ if (SFP_RATE == 0) begin : sfp_mac
.STAT_RX_LEVEL(1),
.STAT_ID_BASE((16+16)*3),
.STAT_UPDATE_PERIOD(1024),
.STAT_STR_EN(1),
.STAT_PREFIX_STR("SFP3"),
.TX_FIFO_DEPTH(16384),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(16384),
@@ -632,7 +640,9 @@ end else begin : sfp_mac
.STAT_TX_LEVEL(1),
.STAT_RX_LEVEL(1),
.STAT_ID_BASE(0),
.STAT_UPDATE_PERIOD(1024)
.STAT_UPDATE_PERIOD(1024),
.STAT_STR_EN(1),
.STAT_PREFIX_STR('{"SFP0", "SFP1", "SFP2", "SFP3"})
)
sfp_mac_inst (
.xcvr_ctrl_clk(clk_125mhz),

9
example/ZCU106/fpga/rtl/fpga_core.sv
View File

@@ -211,6 +211,8 @@ if (SFP_RATE == 0) begin : sfp_mac
.STAT_RX_LEVEL(1),
.STAT_ID_BASE((16+16)*0),
.STAT_UPDATE_PERIOD(1024),
.STAT_STR_EN(1),
.STAT_PREFIX_STR("SFP0"),
.TX_FIFO_DEPTH(16384),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(16384),
@@ -291,6 +293,8 @@ if (SFP_RATE == 0) begin : sfp_mac
.STAT_RX_LEVEL(1),
.STAT_ID_BASE((16+16)*1),
.STAT_UPDATE_PERIOD(1024),
.STAT_STR_EN(1),
.STAT_PREFIX_STR("SFP1"),
.TX_FIFO_DEPTH(16384),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(16384),
@@ -446,7 +450,10 @@ end else begin : sfp_mac
.STAT_TX_LEVEL(1),
.STAT_RX_LEVEL(1),
.STAT_ID_BASE(0),
.STAT_UPDATE_PERIOD(1024)
.STAT_UPDATE_PERIOD(1024)//,
// disabled due to verilator bug
// .STAT_STR_EN(1),
// .STAT_PREFIX_STR('{"SFP0", "SFP1"})
)
sfp_mac_inst (
.xcvr_ctrl_clk(clk_125mhz),

4
example/ZCU111/fpga/rtl/fpga_core.sv
View File

@@ -254,7 +254,9 @@ taxi_eth_mac_25g_us #(
.STAT_TX_LEVEL(1),
.STAT_RX_LEVEL(1),
.STAT_ID_BASE(0),
.STAT_UPDATE_PERIOD(1024)
.STAT_UPDATE_PERIOD(1024),
.STAT_STR_EN(1),
.STAT_PREFIX_STR('{"SFP0", "SFP1", "SFP2", "SFP3"})
)
sfp_mac_inst (
.xcvr_ctrl_clk(clk_125mhz),