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38 lines
1.2 KiB
Markdown
38 lines
1.2 KiB
Markdown
# Taxi Example Design for Arty A7
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## Introduction
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This example design targets the Digilent Arty A7 FPGA board.
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The design places a looped-back MAC on the BASE-T port, as well as a looped-back UART on the USB UART.
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* USB UART
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* Looped-back UART
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* RJ-45 Ethernet port with TI DP83848J PHY
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* Looped-back MAC via MII
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## Board details
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* FPGA: XC7A35TICSG324-1L
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* USB UART: FTDI FT2232H
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* PHY: TI DP83848J via MII
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## Licensing
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* Toolchain
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* Vivado Standard (enterprise license not required)
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* IP
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* No licensed vendor IP or 3rd party IP
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## How to build
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Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
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## How to test
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Run `make program` to program the board with Vivado.
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To test the looped-back UART, use any serial terminal software like minicom, screen, etc. The looped-back UART will echo typed text back without modification.
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To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback. Do not connect the looped-back MAC to a network as the reflected packets may cause problems.
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