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47 lines
1.9 KiB
Markdown
47 lines
1.9 KiB
Markdown
# Taxi Example Design for KC705
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## Introduction
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This example design targets the Xilinx KC705 FPGA board.
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The design places looped-back MACs on both the BASE-T port as well as the SFP+ cage, as well as a looped-back UART on on the USB UART connection.
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* USB UART
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* Looped-back UART
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* RJ-45 Ethernet port with Marvell 88E1111 PHY
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* Looped-back MAC via GMII
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* Looped-back MAC via RGMII
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* Looped-back MAC via SGMII via Xilinx PCS/PMA core and GTX transceiver
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* SFP+ cage
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* Looped-back 1000BASE-X via Xilinx PCS/PMA core and GTX transceiver
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## Board details
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* FPGA: XC7K325T-2FFG900C
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* 1000BASE-T PHY: Marvell 88E1111 via GMII, RGMII, or SGMII
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* 1000BASE-X PHY: Xilinx PCS/PMA core via GTX transceiver
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## How to build
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Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
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## Board configuration
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Several jumpers must be configured to configure the PHY chip for the appropriate mode.
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| Mode | J29 | J30 | J64 |
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| -------- | ---- | ---- | ---- |
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| GMII/MII | 1-2 | 1-2 | open |
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| RGMII | 1-2 | open | 1-2 |
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| SGMII | 2-3 | 2-3 | open |
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Also, note that version 1.0 of the KC705 has the SFP+ TX and RX connections polarity-inverted. Version 1.1 has this fixed. This setting is controlled via a top-level parameter setting that is configurable via config.tcl, so ensure to use a design matching the board revision.
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## How to test
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Run `make program` to program the board with Vivado.
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To test the looped-back UART, use any serial terminal software like minicom, screen, etc. The looped-back UART will echo typed text back without modification.
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To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback. Do not connect the looped-back MAC to a network as the reflected packets may cause problems.
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