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56 lines
1.8 KiB
Markdown
56 lines
1.8 KiB
Markdown
# Taxi Example Design for Alveo
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## Introduction
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This example design targets the Xilinx Alveo series.
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The design places looped-back MACs on the Ethernet ports as well as a looped-back UART on on the USB UART connections.
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* USB UART
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* Looped-back UART
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* DSFP/QSFP28
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* Looped-back 10GBASE-R or 25GBASE-R MACs via GTY transceivers
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## Board details
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* FPGA
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* AU45N/SN1000: xcu26-vsva1365-2LV-e
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* AU50: xcu50-fsvh2104-2-e
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* AU55C: xcu55c-fsvh2892-2L-e
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* AU55N/C1100: xcu55n-fsvh2892-2L-e
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* AU200: xcu200-fsgd2104-2-e
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* AU250: xcu250-fsgd2104-2-e
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* AU280: xcu280-fsvh2892-2L-e
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* VCU1525: xcvu9p-fsgd2104-2L-e
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* X3/X3522: xcux35-vsva1365-3-e
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* USB UART
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* AU45N/SN1000: FTDI FT4232H (DMB-2)
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* AU50: FTDI FT4232H (3 via DMB-1)
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* AU55C: FTDI FT4232H (2 onboard, all 3 via DMB-1)
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* AU55N/C1100: FTDI FT4232H (2 onboard, all 3 via DMB-1)
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* AU200: FTDI FT4232H
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* AU250: FTDI FT4232H
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* AU280: FTDI FT4232H
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* VCU1525: FTDI FT4232H
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* X3/X3522: FTDI FT4232H (DMB-2)
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* 25GBASE-R PHY: Soft PCS with GTY transceivers
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## Licensing
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* Toolchain
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* Vivado Standard (enterprise license not required)
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* IP
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* No licensed vendor IP or 3rd party IP
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## How to build
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Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
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## How to test
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Run `make program` to program the board with Vivado.
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To test the looped-back UART, use any serial terminal software like minicom, screen, etc. The looped-back UART will echo typed text back without modification.
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To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback. Do not connect the looped-back MAC to a network as the reflected packets may cause problems.
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