Alex Forencich 0220b73b8f eth: Fix transcoding of signal ordered sets in XGMII-BASE-R encode module ...

Signed-off-by: Alex Forencich <alex@alexforencich.com>

2026-06-19 16:49:32 -07:00

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apb

apb: Update APB interconnect to support arbitration between multiple upstream devices

2026-03-19 22:05:27 -07:00

axi

axi: Clean up user signal width handling in AXI RAM IF modules

2026-03-20 00:06:23 -07:00

axis

axis: Add AXI stream padding module and testbench

2026-05-11 15:22:56 -07:00

cndm

cndm: Update designs

2026-05-12 12:09:48 -07:00

cndm_proto

cndm_proto: Update designs

2026-05-12 01:47:00 -07:00

dma

dma: Clean up array init

2026-03-08 14:41:24 -07:00

eth

eth: Fix transcoding of signal ordered sets in XGMII-BASE-R encode module

2026-06-19 16:49:32 -07:00

hip/rtl/us

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io/rtl

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lfsr

lfsr: Update LFSR module to support shifting the state before/after shifting the data, including backwards shifts

2026-05-11 15:02:30 -07:00

lss

lss: Add tBUF setting to I2C master to insert bus idle time before starts and repeated starts

2026-03-18 12:30:11 -07:00

math

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pcie

pcie: Remove extra APB idle cycles

2026-03-12 16:57:22 -07:00

prim

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ptp

ptp: Remove extra APB idle cycles

2026-03-12 16:57:34 -07:00

pyrite

pyrite: Use APB 1S interconnect

2026-03-19 19:15:14 -07:00

stats

stats: Clean up array init

2026-03-08 14:43:31 -07:00

sync

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xfcp

xfcp: Fix APB implementation

2026-03-13 01:23:31 -07:00

zircon

zircon: Reorganize metadata for better rules engine interface

2026-04-07 15:47:43 -07:00