mirror of
https://github.com/fpganinja/taxi.git
synced 2025-12-09 17:08:38 -08:00
37 lines
1.2 KiB
Markdown
37 lines
1.2 KiB
Markdown
# Taxi Example Design for ZCU106
|
|
|
|
## Introduction
|
|
|
|
This example design targets the Xilinx ZCU106 FPGA board.
|
|
|
|
The design places looped-back MACs on the SFP+ ports as well as a looped-back UART on on the USB UART connection.
|
|
|
|
* USB UART
|
|
* Looped-back UART
|
|
* QSFP28
|
|
* Looped-back 10GBASE-R MACs via GTH transceivers
|
|
|
|
## Board details
|
|
|
|
* FPGA: xczu7ev-ffvc1156-2-e
|
|
* 10GBASE-R PHY: Soft PCS with GTH transceivers
|
|
|
|
## Licensing
|
|
|
|
* Toolchain
|
|
* Vivado Standard (enterprise license not required)
|
|
* IP
|
|
* No licensed vendor IP or 3rd party IP
|
|
|
|
## How to build
|
|
|
|
Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
|
|
|
|
## How to test
|
|
|
|
Run `make program` to program the board with Vivado.
|
|
|
|
To test the looped-back UART, use any serial terminal software like minicom, screen, etc. The looped-back UART will echo typed text back without modification.
|
|
|
|
To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback. Do not connect the looped-back MAC to a network as the reflected packets may cause problems.
|