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Created with Raphaël 2.2.07May226Sep2312Jun1021Oct19Aug131Aug23Oct6Oct12Aug8Oct227Sep8Jun22May162Add debug output signalsadd-REadd-REAdd RE signalOnly latch DI if RDYmastermasterFix for split phase65C02: fix a bug with TSB/TRB when RDY usedMerge remote-tracking branch 'upstream/master'Fix synthesis warnings, add SYNC outputRemove trailing whitespaceUpdated READMEAdded fix for 1-cycle RDY bugUpdated README and 65C02 CopyrightArlet 65C02 WIP: Implement correct 65C02 BCD N/Z flags (optional, disabled)Arlet 65C02 WIP: Implement NOPs (optional)Arlet 65C02 WIP: Implement JMP (,X)Arlet 65C02 WIP: Implement TSB/TXBArlet 65C02 WIP: Implement BIT zpx, absx, immArlet 65C02 WIP: Implement STZArlet 65C02 WIP: CosmeticArlet 65C02 WIP: Implement (zp) addressing modeArlet 65C02 WIP: Implement INC A, DEC AArlet 65C02 WIP: Implement BRAArlet 65C02 WIP: Implement PLX,PHX,PLY,PHYArlet 65C02 WIP: Copied cpu.v to cpu_65c02.v and renamed moduleAdded clarification of memory interfacefix for bit/logic verilator keywordsSpeed up ALU pathFix syntax errorRemoved $display debugFixed verification bugsAdded RDY term to AB Hold updatefixed typoMake SEI/CLI take effect one cycle earlier.Do not set ABH/ABL in push/pull to avoid wrong PC being pushed if IRQ followsFixed 'load_reg' for CLC/SEC/CLI/SEI/CLV/CLD/SEDFixed '=' back to '<=' for 'backwards' signal.Replaced <= by = in combinatorial blocksAdded support for RDYfirst commit