Resolve "Be able to access entire memory"

Closes #8

See merge request !7

Resolve "Support block reads"

Closes #6

See merge request !6

You need to figure out how to load only certain portions at a time.

Resolve "Support ACMD"

Closes #5

See merge request !5

Resolve "Support CMD8"

Closes #4

See merge request !2

Try and find loop

Closes #1

See merge request !4

Resolve "Create basic device"

Closes #1

See merge request !3

Resolve "Create basic device"

Closes #1

See merge request !1

This is cause the top level testbench is named sim_top, and it is not
smart about choosing its files. It will find both the top level sim_top
and also ours, so we just name it something else for now.

In the future we should be smarter and only choose design files for
these sub modules