Factor out verilog-6502 submodule

This commit is contained in:
2026-04-18 18:55:05 -07:00
parent db61ca2d74
commit 06f933fa56
6 changed files with 1543 additions and 16 deletions

3
.gitmodules vendored
View File

@@ -1,6 +1,3 @@
[submodule "sim/sub/taxi"]
path = sim/sub/taxi
url = git@git.byronlathi.com:bslathi19/taxi.git
[submodule "sim/sub/verilog-6502"]
path = sim/sub/verilog-6502
url = git@git.byronlathi.com:third-party/verilog-6502.git