Reviewed-on: #2 Co-authored-by: Byron Lathi <byron@byronlathi.com> Co-committed-by: Byron Lathi <byron@byronlathi.com>
Description
No description provided
Languages
SystemVerilog
40.2%
Verilog
37.1%
Python
20.6%
Assembly
1.6%
Makefile
0.3%
Other
0.2%