bslathi19/verilog6502
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32bit (#2)

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Reviewed-on: #2
Co-authored-by: Byron Lathi <byron@byronlathi.com>
Co-committed-by: Byron Lathi <byron@byronlathi.com>
This commit was merged in pull request #2.
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Byron Lathi
2026-05-09 15:33:54 -07:00
committed by bslathi19
parent 06f933fa56
commit 089df744aa
21 changed files with 1645 additions and 284 deletions
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init_env.sh
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@@ -7,4 +7,6 @@ pip install -r requirements.txt
export PYTHON3=$(which python)
module load verilator
module load verilator
export CC65_BIN="$REPO_TOP/../cc65/bin/"