Reviewed-on: #2
Co-authored-by: Byron Lathi <byron@byronlathi.com>
Co-committed-by: Byron Lathi <byron@byronlathi.com>
This commit was merged in pull request #2.
This commit is contained in:
2026-05-09 15:33:54 -07:00
committed by bslathi19
parent 06f933fa56
commit 089df744aa
21 changed files with 1645 additions and 284 deletions

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tests:
- name: "cpu_65c02"
toplevel: "cpu_65c02"
modules:
- "verilog6502_32bit_asm_test"
sources: "sources.list"
waves: True
defines:
SIM: "hi"