Add indirect indexed

sim/verilog6502_32bit_test.py

@@ -401,5 +401,73 @@ async def test_indexed_indirect(dut):
         (0xabcdbef2, False, None),            # store takes extra cycle
         (0xabcdbef2, True, 0xAB),             # write data
     ]
-    
-    await check_instruction_sequence(dut, expected_cpu_outputs)
+
+    await check_instruction_sequence(dut, expected_cpu_outputs)
+
+@cocotb.test
+async def test_indirect_indexed(dut):
+    cocotb.start_soon(Clock(dut.clk, CLK_PERIOD, unit="ns").start())
+    cocotb.start_soon(handle_memory(dut))
+
+    write_dword(0xfffffff4, 0x200)
+
+
+    # ldx #4
+    # lda ($04,x)
+    # inc
+    # ldx #8
+    # sta ($04,x)
+    write_bytes(0x200, [0xa2, 0x04])
+    write_bytes(0x202, [0xa1, 0x04])
+    write_bytes(0x204, [0x1a])
+    write_bytes(0x205, [0xa2, 0x08])
+    write_bytes(0x207, [0x81, 0x04])
+    write_byte(0x209, 0xcb)
+
+    write_dword(0x08, 0xfeedf00d)
+    write_dword(0x0c, 0xf00d600d)
+
+    write_byte(0xfeedf00d, 0x69)
+
+    dut.RDY.value = Immediate(1)
+
+    dut.reset.value = Immediate(1)
+    for _ in range(10):
+        await RisingEdge(dut.clk)
+    dut.reset.value = 0
+
+    expected_cpu_outputs = [
+        None,   # ignore reset sequence
+        None,
+        None,
+        None,
+        None,
+        None,
+        None,
+        None,
+        None,
+        (0x00000200, False, None),            # ldx #4
+        (0x00000201, False, None),            # Immediate
+        (0x00000202, False, None),            # lda ($04,x)
+        (0x00000203, False, None),            # ZP index
+        (0x00000004, False, None),            # Compute ZP index
+        (0x00000008, False, None),            # zp addr 0
+        (0x00000009, False, None),            # zp addr 1
+        (0x0000000a, False, None),            # zp addr 2
+        (0x0000000b, False, None),            # zp addr 3
+        (0xfeedf00d, False, None),            # fetch data
+        (0x00000204, False, None),            # iny
+        (0x00000205, False, None),            # iny
+        (0x00000205, False, None),            # inc
+        (0x00000206, False, None),            # inc
+        (0x00000207, False, None),            # sta ($04),y
+        (0x00000208, False, None),            # ZP index
+        (0x00000004, False, None),            # Compute ZP index
+        (0x0000000c, False, None),            # zp addr 0
+        (0x0000000d, False, None),            # zp addr 1
+        (0x0000000e, False, None),            # zp addr 2
+        (0x0000000f, False, None),            # zp addr 3
+        (0xf00d600d, True, 0x6a),             # write data
+    ]
+
+    await check_instruction_sequence(dut, expected_cpu_outputs)