Get it roughly working
This commit is contained in:
299
sim/application_wrapper/cache/application_wrapper_cache_miss_handler_test.py
vendored
Normal file
299
sim/application_wrapper/cache/application_wrapper_cache_miss_handler_test.py
vendored
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@@ -0,0 +1,299 @@
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import cocotb
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from cocotb.handle import LogicArray, Array, Immediate
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from cocotb.clock import Clock
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from cocotb.triggers import ReadOnly, NextTimeStep, RisingEdge, Timer
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import logging
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import random
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from enum import IntEnum
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logger = logging.getLogger()
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logger.setLevel(logging.INFO)
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CLK_PERIOD = 5
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SETS = 64
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WAYS = 4
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TAG_WIDTH = 20
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data_arrays = [{}, {}, {}, {}]
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meta_arrays = [{}, {}, {}, {}]
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lru_array = {}
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class MesiState(IntEnum):
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MESI_INVALID = 0
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MESI_SHARED = 1,
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MESI_EXCLUSIVE = 2,
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MESI_MODIFIED = 3,
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def write_cacheline(index: int, way: int, data: bytes, mesi_state: MesiState, tag: int):
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data_arrays[way][index] = data
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meta_arrays[way][index] = (mesi_state << 20) | tag
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async def handle_cache_arrays(dut):
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while True:
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await RisingEdge(dut.i_clk)
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if dut.o_write_valid.value:
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index = int(dut.o_write_index.value)
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write_enables = [bool(int(dut.o_write_valid.value) & (1 << i)) for i in range(4)]
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write_data = dut.o_write_data.value.to_bytes(byteorder="little")
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write_meta = int(dut.o_write_meta.value)
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logger.debug(f"Write Valid: {index=} {write_enables=} {write_data=} {write_meta=:#x}")
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for data_array, meta_array, write_enable in zip(data_arrays, meta_arrays, write_enables):
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if write_enable:
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data_array[index] = write_data
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meta_array[index] = write_meta
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if dut.o_read_valid.value:
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index = int(dut.o_read_index.value)
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logger.debug(f"Read Valid: {index=}")
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read_data = [LogicArray.from_bytes(data[index], byteorder="little") for data in data_arrays]
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read_meta = [meta[index] for meta in meta_arrays]
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dut.i_read_data.value = read_data
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dut.i_read_meta.value = read_meta
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async def handle_lru_arrays(dut):
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while True:
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await RisingEdge(dut.i_clk)
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if dut.o_lru_write_valid.value:
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logger.debug("lru write")
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lru_write_index = int(dut.o_lru_write_index.value)
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lru_write_data = int(dut.o_lru_write_data.value)
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lru_array[lru_write_index] = lru_write_data
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if dut.o_lru_read_valid.value:
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logger.debug("lru read")
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lru_read_index = int(dut.o_lru_read_index.value)
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dut.i_lru_read_data.value = lru_array[lru_read_index]
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async def handle_writeback(dut):
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dut.i_writeback_done.value = 0
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while True:
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await RisingEdge(dut.i_clk)
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if not dut.o_writeback_valid.value:
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continue
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logger.info("Writeback valid")
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await RisingEdge(dut.i_clk)
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await RisingEdge(dut.i_clk)
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dut.i_writeback_done.value = 1
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await RisingEdge(dut.i_clk)
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dut.i_writeback_done.value = 0
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async def handle_bus_interface(dut):
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dut.i_memory_done.value = 0
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dut.i_memory_resp.value = 0
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while True:
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await RisingEdge(dut.i_clk)
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if not dut.o_memory_valid.value:
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continue
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logger.debug("Bus Interface Access")
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await RisingEdge(dut.i_clk)
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await RisingEdge(dut.i_clk)
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dut.i_memory_done.value = 1
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dut.i_memory_resp.value = 2
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await RisingEdge(dut.i_clk)
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dut.i_memory_done.value = 0
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dut.i_memory_resp.value = 0
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@cocotb.test
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async def test_sanity(dut):
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# Request a read from the cache, then request a write to the cache
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cocotb.start_soon(Clock(dut.i_clk, CLK_PERIOD, unit="ns").start())
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cocotb.start_soon(handle_cache_arrays(dut))
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dut.i_rst.value = Immediate(1)
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for _ in range(10):
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await RisingEdge(dut.i_clk)
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dut.i_rst.value = 0
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await RisingEdge(dut.o_rdy)
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for way in range(WAYS):
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for index in range(SETS):
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write_cacheline(index, way, bytes([0] * 64), MesiState.MESI_EXCLUSIVE, 0)
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for i in range(32):
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if not dut.o_rdy.value:
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continue
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dut.i_cpu_tag.value = 0
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dut.i_cpu_index.value = i
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dut.i_cpu_offset.value = 0
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dut.i_rdy.value = 1
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dut.i_cpu_we.value = 0
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await RisingEdge(dut.i_clk)
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@cocotb.test
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async def test_clean_eviction(dut):
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cocotb.start_soon(Clock(dut.i_clk, CLK_PERIOD, unit="ns").start())
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cocotb.start_soon(handle_cache_arrays(dut))
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cocotb.start_soon(handle_lru_arrays(dut))
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cocotb.start_soon(handle_writeback(dut))
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cocotb.start_soon(handle_bus_interface(dut))
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dut.i_rst.value = Immediate(1)
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for _ in range(10):
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await RisingEdge(dut.i_clk)
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dut.i_rst.value = 0
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await RisingEdge(dut.o_rdy)
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INDEX = 2
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# Write with tag 0x55
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for way in range(WAYS):
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write_cacheline(INDEX, way, bytes([0xaa] * 64), MesiState.MESI_SHARED, way+1)
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# read with tag 0xaa
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dut.i_cpu_tag.value = 0x0
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dut.i_cpu_index.value = INDEX
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dut.i_cpu_offset.value = 2
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dut.i_rdy.value = 1
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dut.i_cpu_we.value = 0
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await RisingEdge(dut.i_clk)
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dut.i_cpu_tag.value = 0xaa
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await RisingEdge(dut.i_clk)
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dut.i_cpu_tag.value = 0
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await Timer(1, "us")
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@cocotb.test
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async def test_eviction(dut):
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cocotb.start_soon(Clock(dut.i_clk, CLK_PERIOD, unit="ns").start())
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cocotb.start_soon(handle_cache_arrays(dut))
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cocotb.start_soon(handle_lru_arrays(dut))
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cocotb.start_soon(handle_writeback(dut))
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cocotb.start_soon(handle_bus_interface(dut))
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dut.i_rst.value = Immediate(1)
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for _ in range(10):
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await RisingEdge(dut.i_clk)
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dut.i_rst.value = 0
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await RisingEdge(dut.o_rdy)
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INDEX = 2
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# Write with tag 0x55
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for way in range(WAYS):
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write_cacheline(INDEX, way, bytes([0xaa] * 64), MesiState.MESI_MODIFIED, way+1)
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# read with tag 0xaa
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dut.i_cpu_tag.value = 0x0
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dut.i_cpu_index.value = INDEX
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dut.i_cpu_offset.value = 2
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dut.i_rdy.value = 1
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dut.i_cpu_we.value = 0
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await RisingEdge(dut.i_clk)
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dut.i_cpu_tag.value = 0xaa
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await RisingEdge(dut.i_clk)
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dut.i_cpu_tag.value = 0
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await Timer(1, "us")
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@cocotb.test
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async def test_request_ownership(dut):
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cocotb.start_soon(Clock(dut.i_clk, CLK_PERIOD, unit="ns").start())
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cocotb.start_soon(handle_cache_arrays(dut))
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cocotb.start_soon(handle_lru_arrays(dut))
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cocotb.start_soon(handle_writeback(dut))
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cocotb.start_soon(handle_bus_interface(dut))
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dut.i_rst.value = Immediate(1)
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for _ in range(10):
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await RisingEdge(dut.i_clk)
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dut.i_rst.value = 0
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await RisingEdge(dut.o_rdy)
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INDEX = 2
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# Write with tag way + 1
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for way in range(WAYS):
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write_cacheline(INDEX, way, bytes([0xaa] * 64), MesiState.MESI_SHARED, way+1)
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# write with tag 0x2
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dut.i_cpu_tag.value = 0
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dut.i_cpu_index.value = INDEX
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dut.i_cpu_offset.value = 2
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dut.i_cpu_data.value = 0xaa
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dut.i_rdy.value = 1
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dut.i_cpu_we.value = 1
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await RisingEdge(dut.i_clk)
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dut.i_cpu_data.value = 0
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dut.i_cpu_tag.value = 2
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await RisingEdge(dut.i_clk)
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dut.i_cpu_tag.value = 0
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await Timer(1, "us")
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@cocotb.test
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async def test_way_read_thrash(dut):
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cocotb.start_soon(Clock(dut.i_clk, CLK_PERIOD, unit="ns").start())
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cocotb.start_soon(handle_cache_arrays(dut))
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cocotb.start_soon(handle_lru_arrays(dut))
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cocotb.start_soon(handle_writeback(dut))
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cocotb.start_soon(handle_bus_interface(dut))
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dut.i_rst.value = Immediate(1)
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for _ in range(10):
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await RisingEdge(dut.i_clk)
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dut.i_rst.value = 0
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await RisingEdge(dut.o_rdy)
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for tag in range(32):
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dut.i_cpu_tag.value = tag
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dut.i_cpu_index.value = 0
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dut.i_cpu_offset.value = 0
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dut.i_rdy.value = 1
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await RisingEdge(dut.i_clk)
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while not dut.o_rdy.value:
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await RisingEdge(dut.i_clk)
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await Timer(1, "us")
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6
sim/application_wrapper/cache/cache.yaml
vendored
6
sim/application_wrapper/cache/cache.yaml
vendored
@@ -5,3 +5,9 @@ tests:
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- "application_wrapper_cache_arrays_test"
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sources: "sources.list"
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waves: True
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- name: "application_wrapper_cache_miss_handler_test"
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toplevel: "application_wrapper_cache_miss_handler"
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modules:
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- "application_wrapper_cache_miss_handler_test"
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sources: "sources.list"
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waves: True
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@@ -1,3 +1,5 @@
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import application_wrapper_cache_pkg::*;
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module application_wrapper_cache_miss_handler #(
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parameter NUM_WAYS = 4,
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parameter NUM_SETS = 64,
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@@ -7,7 +9,7 @@ module application_wrapper_cache_miss_handler #(
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localparam OFFSET_W = 6,
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localparam INDEX_W = $clog2(NUM_SETS),
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localparam TAG_W = 32 - INDEX_W - OFFSET_W,
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localparam LRU_W = NUM_WAYS-1
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localparam LRU_W = NUM_WAYS-1,
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localparam META_W = TAG_W + 2
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) (
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@@ -41,48 +43,89 @@ module application_wrapper_cache_miss_handler #(
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output logic [INDEX_W-1:0] o_lru_read_index,
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output logic o_lru_read_valid,
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input logic [LRU_W-1:0]] i_lru_read_data,
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input logic [LRU_W-1:0] i_lru_read_data,
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output logic [INDEX_W-1:0] o_lru_write_index,
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output logic o_lru_write_valid,
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output logic [LRU_W-1:0]] o_lru_write_data,
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output logic [LRU_W-1:0] o_lru_write_data,
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output logic [DATA_W-1:0] o_writeback_data,
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output logic [31:0] o_writeback_addr,
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output logic o_writeback_valid,
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input logic i_writeback_done,
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output logic [31:0] o_memory_addr,
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output logic o_memory_valid,
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output cache_cmd_e o_memory_cmd,
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input logic [DATA_W-1:0] i_memory_data,
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input logic i_memory_done,
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input cache_resp_e i_memory_resp
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);
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enum logic [3:0] {
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RESET,
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CLEAR_MEMORY,
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IDLE,
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CHECK_VICTIM,
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WRITEBACK,
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WAIT_WRITEBACK_ACK,
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REQUEST_MEMORY,
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WAIT_MEMORY,
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INSTALL_LINE,
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UPDATE_LRU,
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REQUEST_OWNERSHIP
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} state, state_next;
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logic cpu_we_d1;
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logic cpu_i_data_d1;
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logic [INDEX_W-1:0] clear_index, clear_index_next;
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logic [INDEX_W-1:0] cpu_index_d1;
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logic [OFFSET_W-1:0] cpu_offset_d1;
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logic cpu_we_d1;
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logic [CPU_W-1:0] cpu_i_data_d1;
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logic [TAG_W-1:0] cpu_tag_d1;
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logic [INDEX_W-1:0] cpu_index_d1, cpu_index_d2;
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logic [OFFSET_W-1:0] cpu_offset_d1, cpu_offset_d2;
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logic [TAG_W-1:0] cpu_tag_new, cpu_tag_new_next;
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logic [INDEX_W-1:0] cpu_index_new, cpu_index_new_next;
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logic [OFFSET_W-1:0] cpu_offset_new, cpu_offset_new_next;
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logic [$clog2(NUM_WAYS)-1:0] cpu_way_new, cpu_way_new_next;
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logic [7:0] cpu_data_new, cpu_data_new_next;
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logic previous_was_valid, previous_was_valid_next;
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logic way_match_found;
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logic [NUM_WAYS-1:0] way_select_mask;
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logic [$clog2(NUM_WAYS)-1:0] way_select_idx;
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mesi_e mesi;
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logic [TAG_W-1:0] tag;
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logic [31:0] read_req_addr, read_req_addr_next;
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always_ff @(posedge i_clk) begin
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if (i_rst) begin
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state <= IDLE;
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state <= RESET;
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end else begin
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state <= state_next;
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end
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previous_was_valid <= previous_was_valid_next;
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read_req_addr <= read_req_addr_next;
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cpu_offset_new <= cpu_offset_new_next;
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cpu_index_new <= cpu_index_new_next;
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cpu_tag_new <= cpu_tag_new_next;
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cpu_way_new <= cpu_way_new_next;
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cpu_data_new <= cpu_data_new_next;
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clear_index <= clear_index_next;
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cpu_we_d1 <= i_cpu_we;
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cpu_i_data_d1 <= i_cpu_data
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cpu_i_data_d1 <= i_cpu_data;
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cpu_index_d1 <= i_cpu_index;
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cpu_index_d2 <= cpu_index_d1;
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cpu_tag_d1 <= i_cpu_tag;
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cpu_offset_d1 <= i_cpu_offset;
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cpu_offset_d2 <= cpu_offset_d1;
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end
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always_comb begin
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@@ -103,30 +146,72 @@ always_comb begin
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o_lru_write_index = '0;
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o_lru_write_data = '0;
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o_writeback_data = '0;
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o_writeback_addr = '0;
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o_writeback_valid = '0;
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o_memory_addr = '0;
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o_memory_valid = '0;
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o_memory_cmd = CACHE_CMD_NONE;
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way_match_found = '0;
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way_select_mask = '0;
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way_select_idx = '0;
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mesi = MESI_INVALID;
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tag = '0;
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cpu_offset_new_next = cpu_offset_new;
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cpu_index_new_next = cpu_index_new;
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cpu_tag_new_next = cpu_tag_new;
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cpu_way_new_next = cpu_way_new;
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cpu_data_new_next = cpu_data_new;
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read_req_addr_next = read_req_addr;
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clear_index_next = clear_index;
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previous_was_valid_next = previous_was_valid;
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state_next = state;
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case (state)
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RESET: begin
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state_next = CLEAR_MEMORY;
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clear_index_next = '0;
|
||||
previous_was_valid_next = '0;
|
||||
end
|
||||
|
||||
CLEAR_MEMORY: begin
|
||||
o_write_valid = '1;
|
||||
o_write_data = '0;
|
||||
o_write_meta = {MESI_INVALID, (TAG_W)'('0)};
|
||||
o_write_index = clear_index;
|
||||
|
||||
o_lru_write_index = clear_index;
|
||||
o_lru_write_data = '0;
|
||||
o_lru_write_valid = '1;
|
||||
|
||||
clear_index_next = clear_index + 1;
|
||||
if (clear_index_next == '0) begin
|
||||
state_next = IDLE;
|
||||
end
|
||||
end
|
||||
|
||||
IDLE: begin
|
||||
// by default, o_rdy is 1 unless something is wrong
|
||||
o_rdy = '1;
|
||||
|
||||
// Read from arrays
|
||||
o_read_index = i_cpu_index;
|
||||
o_read_valid = i_rdy;
|
||||
|
||||
o_lru_read_index = i_cpu_index;
|
||||
o_lru_read_valid = i_rdy;
|
||||
|
||||
if (previous_was_valid) begin
|
||||
// data from previous cycle that was read from arrays
|
||||
way_match_found = '0;
|
||||
way_select_mask = '0;
|
||||
for (int i; i < NUM_WAYS; i++) begin
|
||||
for (int i = 0; i < NUM_WAYS; i++) begin
|
||||
{mesi, tag} = i_read_meta[i];
|
||||
if (tag == i_cpu_tag && mesi != MESI_INVALID) begin
|
||||
way_match_found = '1;
|
||||
way_select_mask[i] = '1;
|
||||
way_select_idx = 2'(i);
|
||||
break;
|
||||
end
|
||||
end
|
||||
@@ -139,19 +224,30 @@ always_comb begin
|
||||
// If we are in S then we need to request ownership before
|
||||
// we can modify it.
|
||||
if (mesi == MESI_MODIFIED || mesi == MESI_EXCLUSIVE) begin
|
||||
o_write_data = i_read_data;
|
||||
o_write_data[cpu_offset_d1 +: 8] = cpu_i_data_d1;
|
||||
o_write_data = i_read_data[way_select_idx];
|
||||
o_write_data[cpu_offset_d1*8 +: CPU_W] = cpu_i_data_d1;
|
||||
o_write_meta = {MESI_MODIFIED, i_cpu_tag};
|
||||
o_write_valid = way_select_mask;
|
||||
o_write_index = cpu_index_d1;
|
||||
|
||||
end else begin
|
||||
o_rdy = '0;
|
||||
|
||||
o_memory_addr = {i_cpu_tag, cpu_index_d1, (OFFSET_W)'('0)};
|
||||
o_memory_cmd = CACHE_CMD_CLEAN_UNIQUE;
|
||||
o_memory_valid = '1;
|
||||
|
||||
cpu_offset_new_next = cpu_offset_d1;
|
||||
cpu_index_new_next = cpu_index_d1;
|
||||
cpu_tag_new_next = i_cpu_tag;
|
||||
cpu_way_new_next = way_select_idx;
|
||||
cpu_data_new_next = cpu_i_data_d1;
|
||||
|
||||
state_next = REQUEST_OWNERSHIP;
|
||||
end
|
||||
end else begin
|
||||
// Send the data to the CPU
|
||||
o_cpu_data = i_read_data[cpu_offset_d1 +: 8];
|
||||
o_cpu_data = i_read_data[way_select_idx][cpu_offset_d1*8 +: CPU_W];
|
||||
end
|
||||
|
||||
// update lru
|
||||
@@ -181,12 +277,188 @@ always_comb begin
|
||||
o_lru_write_data[0] = '0;
|
||||
o_lru_write_data[2] = '0;
|
||||
end
|
||||
endcase
|
||||
|
||||
default: begin
|
||||
end
|
||||
endcase
|
||||
end else begin
|
||||
o_rdy = '0;
|
||||
state_next = CHECK_VICTIM;
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
// Read from arrays
|
||||
o_read_index = i_cpu_index;
|
||||
o_read_valid = i_rdy & o_rdy;
|
||||
|
||||
o_lru_read_index = i_cpu_index;
|
||||
o_lru_read_valid = i_rdy & o_rdy;
|
||||
|
||||
previous_was_valid_next = '1;
|
||||
end
|
||||
|
||||
REQUEST_OWNERSHIP: begin
|
||||
if (i_memory_done) begin
|
||||
// write to the cacheline here.
|
||||
o_write_data = i_read_data[cpu_way_new];
|
||||
o_write_data[cpu_offset_new*8 +: CPU_W] = cpu_data_new;
|
||||
o_write_meta = {MESI_MODIFIED, cpu_tag_new};
|
||||
o_write_valid = (1 << cpu_way_new);
|
||||
o_write_index = cpu_index_new;
|
||||
state_next = IDLE;
|
||||
|
||||
// update lru
|
||||
// start by copying the read data, then change the bits
|
||||
// based on what we matched.
|
||||
o_lru_write_index = cpu_index_new;
|
||||
o_lru_write_data = i_lru_read_data;
|
||||
o_lru_write_valid = '1;
|
||||
|
||||
case (1 << cpu_way_new)
|
||||
4'b0001: begin
|
||||
o_lru_write_data[0] = '1;
|
||||
o_lru_write_data[1] = '1;
|
||||
end
|
||||
|
||||
4'b0010: begin
|
||||
o_lru_write_data[0] = '1;
|
||||
o_lru_write_data[1] = '0;
|
||||
end
|
||||
|
||||
4'b0100: begin
|
||||
o_lru_write_data[0] = '0;
|
||||
o_lru_write_data[2] = '1;
|
||||
end
|
||||
|
||||
4'b1000: begin
|
||||
o_lru_write_data[0] = '0;
|
||||
o_lru_write_data[2] = '0;
|
||||
end
|
||||
|
||||
default: begin
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
CHECK_VICTIM: begin
|
||||
// first use the LRU, then overwrite if there was an invalid way
|
||||
|
||||
way_select_idx[0] = i_lru_read_data[0];
|
||||
way_select_idx[1] = way_select_idx[0] ? i_lru_read_data[2] : i_lru_read_data[1];
|
||||
|
||||
for (int i = 0; i < NUM_WAYS; i++) begin
|
||||
{mesi, tag} = i_read_meta[i];
|
||||
if (mesi == MESI_INVALID) begin
|
||||
way_select_idx = 2'(i);
|
||||
break;
|
||||
end
|
||||
end
|
||||
|
||||
{mesi, tag} = i_read_meta[way_select_idx];
|
||||
|
||||
if (mesi == MESI_MODIFIED) begin
|
||||
o_writeback_data = i_read_data[way_select_idx];
|
||||
o_writeback_addr = {tag, cpu_index_d2, (OFFSET_W)'('0)};
|
||||
o_writeback_valid = '1;
|
||||
state_next = WAIT_WRITEBACK_ACK;
|
||||
end else if (mesi == MESI_EXCLUSIVE || mesi == MESI_SHARED) begin
|
||||
o_memory_addr = {tag, cpu_index_d2, (OFFSET_W)'('0)};
|
||||
o_memory_valid = '1;
|
||||
o_memory_cmd = CACHE_CMD_EVICT;
|
||||
state_next = WAIT_WRITEBACK_ACK;
|
||||
end else begin
|
||||
state_next = REQUEST_MEMORY;
|
||||
end
|
||||
|
||||
read_req_addr_next = {cpu_tag_d1, cpu_index_d2, (OFFSET_W)'('0)};
|
||||
cpu_offset_new_next = cpu_offset_d2;
|
||||
cpu_index_new_next = cpu_index_d2;
|
||||
cpu_tag_new_next = cpu_tag_d1;
|
||||
cpu_way_new_next = way_select_idx;
|
||||
end
|
||||
|
||||
WAIT_WRITEBACK_ACK: begin
|
||||
// This state is also used when sending the EVICT command,
|
||||
// before sending the read.
|
||||
if (i_writeback_done || i_memory_done) begin
|
||||
state_next = REQUEST_MEMORY;
|
||||
end
|
||||
end
|
||||
|
||||
REQUEST_MEMORY: begin
|
||||
// This state can be put into WAIT_WRITEBACK_ACK and CHECK_VICTIM
|
||||
o_memory_addr = read_req_addr;
|
||||
o_memory_valid = '1;
|
||||
// if the cache hit was a write, we should read unique, so we can be
|
||||
// sure that we are given EXCLUSIVE and can set it to MODIFIED right away
|
||||
o_memory_cmd = CACHE_CMD_READ;
|
||||
state_next = WAIT_MEMORY;
|
||||
end
|
||||
|
||||
WAIT_MEMORY: begin
|
||||
// need to handle if this was a write miss
|
||||
if (i_memory_done) begin
|
||||
o_write_valid = (1 << cpu_way_new);
|
||||
o_write_data = i_memory_data;
|
||||
o_write_index = cpu_index_new;
|
||||
if (i_memory_resp == CACHE_RSP_SHARED) begin
|
||||
o_write_meta = {MESI_SHARED, cpu_tag_new};
|
||||
end else if (i_memory_resp == CACHE_RSP_EXCLUSIVE) begin
|
||||
o_write_meta = {MESI_EXCLUSIVE, cpu_tag_new};
|
||||
end
|
||||
|
||||
o_rdy = '1;
|
||||
o_cpu_data = i_memory_data[cpu_offset_new*8 +: CPU_W];
|
||||
|
||||
// update lru
|
||||
// start by copying the read data, then change the bits
|
||||
// based on what we matched.
|
||||
o_lru_write_index = cpu_index_new;
|
||||
o_lru_write_data = i_lru_read_data;
|
||||
o_lru_write_valid = '1;
|
||||
|
||||
case (1 << cpu_way_new)
|
||||
4'b0001: begin
|
||||
o_lru_write_data[0] = '1;
|
||||
o_lru_write_data[1] = '1;
|
||||
end
|
||||
|
||||
4'b0010: begin
|
||||
o_lru_write_data[0] = '1;
|
||||
o_lru_write_data[1] = '0;
|
||||
end
|
||||
|
||||
4'b0100: begin
|
||||
o_lru_write_data[0] = '0;
|
||||
o_lru_write_data[2] = '1;
|
||||
end
|
||||
|
||||
4'b1000: begin
|
||||
o_lru_write_data[0] = '0;
|
||||
o_lru_write_data[2] = '0;
|
||||
end
|
||||
|
||||
default: begin
|
||||
end
|
||||
endcase
|
||||
|
||||
o_read_index = i_cpu_index;
|
||||
o_read_valid = i_rdy & o_rdy;
|
||||
|
||||
o_lru_read_index = i_cpu_index;
|
||||
o_lru_read_valid = i_rdy & o_rdy;
|
||||
|
||||
state_next = IDLE;
|
||||
end
|
||||
end
|
||||
|
||||
default: begin
|
||||
state_next = IDLE;
|
||||
end
|
||||
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -11,18 +11,25 @@ package application_wrapper_cache_pkg;
|
||||
} page_table_entry_t;
|
||||
|
||||
typedef enum logic [2:0] {
|
||||
CACHE_NONE,
|
||||
CACHE_READ_SHARED,
|
||||
CACHE_READ_UNIQUE,
|
||||
CACHE_WRITE,
|
||||
CACHE_CLEAN_UNIQUE
|
||||
CACHE_CMD_NONE,
|
||||
CACHE_CMD_READ,
|
||||
CAHCE_CMD_READ_UNIQUE,
|
||||
CACHE_CMD_WRITE,
|
||||
CACHE_CMD_CLEAN_UNIQUE,
|
||||
CACHE_CMD_EVICT
|
||||
} cache_cmd_e;
|
||||
|
||||
typedef enum logic [1:0] {
|
||||
MESI_MODIFIED,
|
||||
MESI_EXCLUSIVE,
|
||||
CACHE_RSP_NONE,
|
||||
CACHE_RSP_SHARED,
|
||||
CACHE_RSP_EXCLUSIVE
|
||||
} cache_resp_e;
|
||||
|
||||
typedef enum logic [1:0] {
|
||||
MESI_INVALID,
|
||||
MESI_SHARED,
|
||||
MESI_INVALID
|
||||
MESI_EXCLUSIVE,
|
||||
MESI_MODIFIED
|
||||
} mesi_e;
|
||||
|
||||
endpackage
|
||||
@@ -1,5 +1,6 @@
|
||||
cache/application_wrapper_cache_pkg.sv
|
||||
cache/application_wrapper_cache_arrays.sv
|
||||
cache/application_wrapper_cache_miss_handler.sv
|
||||
cache/application_wrapper_mmu.sv
|
||||
cache/application_wrapper_cache_top.sv
|
||||
|
||||
|
||||
Reference in New Issue
Block a user