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Update wrapper to work with 32 bit addresses

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This commit is contained in:
Byron Lathi
2026-05-08 23:02:39 -07:00
parent 6c47ce12a5
commit 7827bcceeb
10 changed files with 164 additions and 134 deletions
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3
sim/verilog6502_wrapper_test.py
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@@ -33,7 +33,8 @@ async def test_sanity(dut):
await RisingEdge(dut.clk)
# await s_axi.write(0x200, [0x58, 0xa9, 0x00, 0x1a, 0xcb, 0x4c, 0x03, 0x02])
await s_axi.write(0x200, [0xAD, 0x00, 0xE0, 0xAD, 0x01, 0xE0, 0xAD, 0x02, 0xE0, 0xAD, 0x03, 0xE0, 0xAD, 0x04, 0xE0, 0xCB])
# await s_axi.write(0x200, [0xAD, 0x00, 0xE0, 0xAD, 0x01, 0xE0, 0xAD, 0x02, 0xE0, 0xAD, 0x03, 0xE0, 0xAD, 0x04, 0xE0, 0xCB])
await s_axi.write(0x200, [0x80, 0xfe])
cocotb.start_soon(s_axi.read(0x200, 8))

1
src/cpu_65c02.v
View File

@@ -789,6 +789,7 @@ ALU ALU( .clk(clk),
.RDY(RDY) );
always @(posedge clk) begin
if( RDY )
if (alu_sr_enable) begin
if (sr_sel == SR_ALU) begin
alu_sr_0 <= ADD;

33
src/regs/verilog6502_io_regs.rdl
View File

@@ -13,20 +13,27 @@ addrmap verilog6502_io_regs {
sw = rw;
} reset[0:0] = 0x1;
field {
name = "rdy";
desc = "";
hw = r;
sw = rw;
} rdy[1:1] = 0x0;
} core_ctrl @ 0x0;
reg {
name = "AXI Base Address";
name = "Core Status";
desc = "";
field {
name = "val";
name = "rdy_o";
desc = "";
hw = r;
sw = rw;
} val[31:0] = 0x0;
sw = r;
} rdy_o[0:0] = 0x0;
} axi_base_address @ 0x10;
} core_status @ 0x4;
reg {
name = "nmi";
@@ -36,11 +43,11 @@ addrmap verilog6502_io_regs {
desc = "";
hw = r;
sw = rw;
} nmi[31:16] = 0x200;
} nmi @ 0xff8;
} nmi[31:0] = 0x200;
} nmi @ 0xff4;
reg {
name = "reset_brq";
name = "reset";
desc = "";
field {
@@ -48,13 +55,17 @@ addrmap verilog6502_io_regs {
desc = "";
hw = r;
sw = rw;
} reset[15:0] = 0x200;
} reset[31:0] = 0x200;
} rst @ 0xff8;
reg {
name = "brk";
field {
name = "brq";
desc = "";
hw = r;
sw = rw;
} brk[31:16] = 0x200;
} reset_brq @ 0xffc;
} brk[31:0] = 0x200;
} brk @ 0xffc;
};

132
src/regs/verilog6502_io_regs.sv
View File

@@ -87,9 +87,10 @@ module verilog6502_io_regs (
//--------------------------------------------------------------------------
typedef struct {
logic core_ctrl;
logic axi_base_address;
logic core_status;
logic nmi;
logic reset_brq;
logic rst;
logic brk;
} decoded_reg_strb_t;
decoded_reg_strb_t decoded_reg_strb;
logic decoded_err;
@@ -105,9 +106,10 @@ module verilog6502_io_regs (
is_valid_addr = '1; // No valid address check
is_valid_rw = '1; // No valid RW check
decoded_reg_strb.core_ctrl = cpuif_req_masked & (cpuif_addr == 12'h0);
decoded_reg_strb.axi_base_address = cpuif_req_masked & (cpuif_addr == 12'h10);
decoded_reg_strb.nmi = cpuif_req_masked & (cpuif_addr == 12'hff8);
decoded_reg_strb.reset_brq = cpuif_req_masked & (cpuif_addr == 12'hffc);
decoded_reg_strb.core_status = cpuif_req_masked & (cpuif_addr == 12'h4) & !cpuif_req_is_wr;
decoded_reg_strb.nmi = cpuif_req_masked & (cpuif_addr == 12'hff4);
decoded_reg_strb.rst = cpuif_req_masked & (cpuif_addr == 12'hff8);
decoded_reg_strb.brk = cpuif_req_masked & (cpuif_addr == 12'hffc);
decoded_err = '0;
end
@@ -127,29 +129,29 @@ module verilog6502_io_regs (
logic next;
logic load_next;
} reset;
struct {
logic next;
logic load_next;
} rdy;
} core_ctrl;
struct {
struct {
logic [31:0] next;
logic load_next;
} val;
} axi_base_address;
struct {
struct {
logic [15:0] next;
logic load_next;
} nmi;
} nmi;
struct {
struct {
logic [15:0] next;
logic [31:0] next;
logic load_next;
} reset;
} rst;
struct {
logic [15:0] next;
struct {
logic [31:0] next;
logic load_next;
} brk;
} reset_brq;
} brk;
} field_combo_t;
field_combo_t field_combo;
@@ -158,25 +160,25 @@ module verilog6502_io_regs (
struct {
logic value;
} reset;
struct {
logic value;
} rdy;
} core_ctrl;
struct {
struct {
logic [31:0] value;
} val;
} axi_base_address;
struct {
struct {
logic [15:0] value;
} nmi;
} nmi;
struct {
struct {
logic [15:0] value;
logic [31:0] value;
} reset;
} rst;
struct {
logic [15:0] value;
struct {
logic [31:0] value;
} brk;
} brk;
} reset_brq;
} field_storage_t;
field_storage_t field_storage;
@@ -203,37 +205,38 @@ module verilog6502_io_regs (
end
end
assign hwif_out.core_ctrl.reset.value = field_storage.core_ctrl.reset.value;
// Field: verilog6502_io_regs.axi_base_address.val
// Field: verilog6502_io_regs.core_ctrl.rdy
always_comb begin
automatic logic [31:0] next_c;
automatic logic [0:0] next_c;
automatic logic load_next_c;
next_c = field_storage.axi_base_address.val.value;
next_c = field_storage.core_ctrl.rdy.value;
load_next_c = '0;
if(decoded_reg_strb.axi_base_address && decoded_req_is_wr) begin // SW write
next_c = (field_storage.axi_base_address.val.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
if(decoded_reg_strb.core_ctrl && decoded_req_is_wr) begin // SW write
next_c = (field_storage.core_ctrl.rdy.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]);
load_next_c = '1;
end
field_combo.axi_base_address.val.next = next_c;
field_combo.axi_base_address.val.load_next = load_next_c;
field_combo.core_ctrl.rdy.next = next_c;
field_combo.core_ctrl.rdy.load_next = load_next_c;
end
always_ff @(posedge clk) begin
if(rst) begin
field_storage.axi_base_address.val.value <= 32'h0;
field_storage.core_ctrl.rdy.value <= 1'h0;
end else begin
if(field_combo.axi_base_address.val.load_next) begin
field_storage.axi_base_address.val.value <= field_combo.axi_base_address.val.next;
if(field_combo.core_ctrl.rdy.load_next) begin
field_storage.core_ctrl.rdy.value <= field_combo.core_ctrl.rdy.next;
end
end
end
assign hwif_out.axi_base_address.val.value = field_storage.axi_base_address.val.value;
assign hwif_out.core_ctrl.rdy.value = field_storage.core_ctrl.rdy.value;
assign hwif_out.core_status.rdy_o.value = 1'h0;
// Field: verilog6502_io_regs.nmi.nmi
always_comb begin
automatic logic [15:0] next_c;
automatic logic [31:0] next_c;
automatic logic load_next_c;
next_c = field_storage.nmi.nmi.value;
load_next_c = '0;
if(decoded_reg_strb.nmi && decoded_req_is_wr) begin // SW write
next_c = (field_storage.nmi.nmi.value & ~decoded_wr_biten[31:16]) | (decoded_wr_data[31:16] & decoded_wr_biten[31:16]);
next_c = (field_storage.nmi.nmi.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
load_next_c = '1;
end
field_combo.nmi.nmi.next = next_c;
@@ -241,7 +244,7 @@ module verilog6502_io_regs (
end
always_ff @(posedge clk) begin
if(rst) begin
field_storage.nmi.nmi.value <= 16'h200;
field_storage.nmi.nmi.value <= 32'h200;
end else begin
if(field_combo.nmi.nmi.load_next) begin
field_storage.nmi.nmi.value <= field_combo.nmi.nmi.next;
@@ -249,52 +252,52 @@ module verilog6502_io_regs (
end
end
assign hwif_out.nmi.nmi.value = field_storage.nmi.nmi.value;
// Field: verilog6502_io_regs.reset_brq.reset
// Field: verilog6502_io_regs.rst.reset
always_comb begin
automatic logic [15:0] next_c;
automatic logic [31:0] next_c;
automatic logic load_next_c;
next_c = field_storage.reset_brq.reset.value;
next_c = field_storage.rst.reset.value;
load_next_c = '0;
if(decoded_reg_strb.reset_brq && decoded_req_is_wr) begin // SW write
next_c = (field_storage.reset_brq.reset.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]);
if(decoded_reg_strb.rst && decoded_req_is_wr) begin // SW write
next_c = (field_storage.rst.reset.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
load_next_c = '1;
end
field_combo.reset_brq.reset.next = next_c;
field_combo.reset_brq.reset.load_next = load_next_c;
field_combo.rst.reset.next = next_c;
field_combo.rst.reset.load_next = load_next_c;
end
always_ff @(posedge clk) begin
if(rst) begin
field_storage.reset_brq.reset.value <= 16'h200;
field_storage.rst.reset.value <= 32'h200;
end else begin
if(field_combo.reset_brq.reset.load_next) begin
field_storage.reset_brq.reset.value <= field_combo.reset_brq.reset.next;
if(field_combo.rst.reset.load_next) begin
field_storage.rst.reset.value <= field_combo.rst.reset.next;
end
end
end
assign hwif_out.reset_brq.reset.value = field_storage.reset_brq.reset.value;
// Field: verilog6502_io_regs.reset_brq.brk
assign hwif_out.rst.reset.value = field_storage.rst.reset.value;
// Field: verilog6502_io_regs.brk.brk
always_comb begin
automatic logic [15:0] next_c;
automatic logic [31:0] next_c;
automatic logic load_next_c;
next_c = field_storage.reset_brq.brk.value;
next_c = field_storage.brk.brk.value;
load_next_c = '0;
if(decoded_reg_strb.reset_brq && decoded_req_is_wr) begin // SW write
next_c = (field_storage.reset_brq.brk.value & ~decoded_wr_biten[31:16]) | (decoded_wr_data[31:16] & decoded_wr_biten[31:16]);
if(decoded_reg_strb.brk && decoded_req_is_wr) begin // SW write
next_c = (field_storage.brk.brk.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
load_next_c = '1;
end
field_combo.reset_brq.brk.next = next_c;
field_combo.reset_brq.brk.load_next = load_next_c;
field_combo.brk.brk.next = next_c;
field_combo.brk.brk.load_next = load_next_c;
end
always_ff @(posedge clk) begin
if(rst) begin
field_storage.reset_brq.brk.value <= 16'h200;
field_storage.brk.brk.value <= 32'h200;
end else begin
if(field_combo.reset_brq.brk.load_next) begin
field_storage.reset_brq.brk.value <= field_combo.reset_brq.brk.next;
if(field_combo.brk.brk.load_next) begin
field_storage.brk.brk.value <= field_combo.brk.brk.next;
end
end
end
assign hwif_out.reset_brq.brk.value = field_storage.reset_brq.brk.value;
assign hwif_out.brk.brk.value = field_storage.brk.brk.value;
//--------------------------------------------------------------------------
// Write response
@@ -318,16 +321,19 @@ module verilog6502_io_regs (
readback_data_var = '0;
if(rd_mux_addr == 12'h0) begin
readback_data_var[0] = field_storage.core_ctrl.reset.value;
readback_data_var[1] = field_storage.core_ctrl.rdy.value;
end
if(rd_mux_addr == 12'h10) begin
readback_data_var[31:0] = field_storage.axi_base_address.val.value;
if(rd_mux_addr == 12'h4) begin
readback_data_var[0] = 1'h0;
end
if(rd_mux_addr == 12'hff4) begin
readback_data_var[31:0] = field_storage.nmi.nmi.value;
end
if(rd_mux_addr == 12'hff8) begin
readback_data_var[31:16] = field_storage.nmi.nmi.value;
readback_data_var[31:0] = field_storage.rst.reset.value;
end
if(rd_mux_addr == 12'hffc) begin
readback_data_var[15:0] = field_storage.reset_brq.reset.value;
readback_data_var[31:16] = field_storage.reset_brq.brk.value;
readback_data_var[31:0] = field_storage.brk.brk.value;
end
readback_data = readback_data_var;
readback_done = decoded_req & ~decoded_req_is_wr;

43
src/regs/verilog6502_io_regs_pkg.sv
View File

@@ -11,20 +11,25 @@ package verilog6502_io_regs_pkg;
logic value;
} verilog6502_io_regs__core_ctrl__reset__out_t;
typedef struct {
logic value;
} verilog6502_io_regs__core_ctrl__rdy__out_t;
typedef struct {
verilog6502_io_regs__core_ctrl__reset__out_t reset;
verilog6502_io_regs__core_ctrl__rdy__out_t rdy;
} verilog6502_io_regs__core_ctrl__out_t;
typedef struct {
logic value;
} verilog6502_io_regs__core_status__rdy_o__out_t;
typedef struct {
verilog6502_io_regs__core_status__rdy_o__out_t rdy_o;
} verilog6502_io_regs__core_status__out_t;
typedef struct {
logic [31:0] value;
} verilog6502_io_regs__axi_base_address__val__out_t;
typedef struct {
verilog6502_io_regs__axi_base_address__val__out_t val;
} verilog6502_io_regs__axi_base_address__out_t;
typedef struct {
logic [15:0] value;
} verilog6502_io_regs__nmi__nmi__out_t;
typedef struct {
@@ -32,22 +37,26 @@ package verilog6502_io_regs_pkg;
} verilog6502_io_regs__nmi__out_t;
typedef struct {
logic [15:0] value;
} verilog6502_io_regs__reset_brq__reset__out_t;
logic [31:0] value;
} verilog6502_io_regs__rst__reset__out_t;
typedef struct {
logic [15:0] value;
} verilog6502_io_regs__reset_brq__brk__out_t;
verilog6502_io_regs__rst__reset__out_t reset;
} verilog6502_io_regs__rst__out_t;
typedef struct {
verilog6502_io_regs__reset_brq__reset__out_t reset;
verilog6502_io_regs__reset_brq__brk__out_t brk;
} verilog6502_io_regs__reset_brq__out_t;
logic [31:0] value;
} verilog6502_io_regs__brk__brk__out_t;
typedef struct {
verilog6502_io_regs__brk__brk__out_t brk;
} verilog6502_io_regs__brk__out_t;
typedef struct {
verilog6502_io_regs__core_ctrl__out_t core_ctrl;
verilog6502_io_regs__axi_base_address__out_t axi_base_address;
verilog6502_io_regs__core_status__out_t core_status;
verilog6502_io_regs__nmi__out_t nmi;
verilog6502_io_regs__reset_brq__out_t reset_brq;
verilog6502_io_regs__rst__out_t rst;
verilog6502_io_regs__brk__out_t brk;
} verilog6502_io_regs__out_t;
endpackage

16
src/verilog6502_addr_decoder.sv
View File

@@ -2,7 +2,7 @@ module verilog6502_addr_decoder(
input i_clk,
input i_rst,
input logic [15:0] i_cpu_addr,
input logic [31:0] i_cpu_addr,
input logic [7:0] i_cpu_data,
output logic [7:0] o_cpu_data,
input logic i_cpu_we,
@@ -17,14 +17,14 @@ module verilog6502_addr_decoder(
output logic o_mem_we,
input logic i_mem_rdy,
output logic [15:0] o_external_addr,
output logic [31:0] o_external_addr,
output logic [7:0] o_external_data,
input logic [7:0] i_external_data,
output logic o_external_rd,
output logic o_external_we,
input logic i_external_rdy,
output logic [15:0] o_io_addr,
output logic [11:0] o_io_addr,
output logic [7:0] o_io_data,
input logic [7:0] i_io_data,
output logic o_io_rd,
@@ -88,20 +88,20 @@ always_comb begin
endcase
if (o_cpu_rdy) begin
if (i_cpu_addr < 16'hE000) begin
o_mem_addr = i_cpu_addr;
if (i_cpu_addr < 32'hFFFF) begin
o_mem_addr = i_cpu_addr[15:0];
o_mem_data = i_cpu_data;
o_mem_we = i_cpu_we & o_cpu_rdy;
o_mem_rd = ~i_cpu_we & o_cpu_rdy;
prev_addr_next = MEM;
end else if (i_cpu_addr < 16'hF000) begin
o_external_addr = {4'b0, i_cpu_addr[11:0]};
end else if (i_cpu_addr < 32'hFFFFEFFF) begin
o_external_addr = i_cpu_addr;
o_external_data = i_cpu_data;
o_external_we = i_cpu_we & o_cpu_rdy;
o_external_rd = ~i_cpu_we & o_cpu_rdy;
prev_addr_next = EXT;
end else begin
o_io_addr = {4'b0, i_cpu_addr[11:0]};
o_io_addr = i_cpu_addr[11:0];
o_io_data = i_cpu_data;
o_io_we = i_cpu_we & o_cpu_rdy;
o_io_rd = ~i_cpu_we & o_cpu_rdy;

18
src/verilog6502_apb_adapter.sv
View File

@@ -1,8 +1,10 @@
module verilog6502_apb_adapter(
module verilog6502_apb_adapter #(
parameter ADDR_WIDTH = 32
)(
input i_clk,
input i_rst,
input logic [15:0] i_addr,
input logic [ADDR_WIDTH-1:0] i_addr,
input logic [7:0] i_data,
output logic [7:0] o_data,
input logic i_rd,
@@ -12,10 +14,12 @@ module verilog6502_apb_adapter(
taxi_apb_if.mst m_apb
);
localparam APB_ADDR_WIDTH = m_apb.ADDR_W;
enum logic {IDLE, ENABLE} state, state_next;
logic [15:0] latched_addr, latched_addr_next;
logic [15:0] second_addr, second_addr_next;
logic [ADDR_WIDTH-1:0] latched_addr, latched_addr_next;
logic [ADDR_WIDTH-1:0] second_addr, second_addr_next;
logic second_we, second_rd, second_we_next, second_rd_next;
logic [7:0] latched_data, latched_data_next;
logic [7:0] second_data, second_data_next;
@@ -51,7 +55,7 @@ always_comb begin
IDLE: begin
if (i_rd | i_we) begin
m_apb.pprot = '0;
m_apb.paddr = {16'b0, i_addr} & 32'hfffc; // 32 bit address
m_apb.paddr = APB_ADDR_WIDTH'({i_addr[ADDR_WIDTH-1:2], 2'b0});
m_apb.psel = '1;
m_apb.pwrite = i_we;
m_apb.pstrb = 4'h1 << i_addr[1:0]; // shift based on lower 2 bits
@@ -65,7 +69,7 @@ always_comb begin
latched_pwrite_next = i_we;
end else if (second_rd | second_we) begin
m_apb.pprot = '0;
m_apb.paddr = {16'b0, second_addr} & 32'hfffc; // 32 bit address
m_apb.paddr = APB_ADDR_WIDTH'({second_addr[ADDR_WIDTH-1:2], 2'b0});
m_apb.psel = '1;
m_apb.pwrite = second_we;
m_apb.pstrb = 4'h1 << second_addr[1:0]; // shift based on lower 2 bits
@@ -97,7 +101,7 @@ always_comb begin
second_data_next = i_data;
m_apb.pprot = '0;
m_apb.paddr = {16'b0, latched_addr} & 32'hfffc; // 32 bit address
m_apb.paddr = APB_ADDR_WIDTH'({latched_addr[ADDR_WIDTH-1:2], 2'b0});
m_apb.psel = '1;
m_apb.pwrite = latched_pwrite;
m_apb.pstrb = 4'h1 << latched_addr[1:0]; // shift based on lower 2 bits

6
src/verilog6502_external_memory.sv
View File

@@ -2,15 +2,13 @@ module verilog6502_external_memory (
input i_clk,
input i_rst,
input logic [15:0] i_addr,
input logic [31:0] i_addr,
input logic [7:0] i_data,
output logic [7:0] o_data,
input logic i_rd,
input logic i_we,
output logic o_rdy,
input logic [31:0] i_axi_base_addr,
taxi_axil_if.wr_mst m_axil_wr,
taxi_axil_if.rd_mst m_axil_rd
@@ -33,7 +31,7 @@ verilog6502_apb_adapter u_internal_apb_adapter (
.m_apb (internal_apb)
);
assign addr_shift_apb.paddr = {i_axi_base_addr[31:12], {internal_apb.paddr[11:0]}};
assign addr_shift_apb.paddr = internal_apb.paddr;
assign addr_shift_apb.pprot = internal_apb.pprot;
assign addr_shift_apb.psel = internal_apb.psel;
assign addr_shift_apb.penable = internal_apb.penable;

2
src/verilog6502_internal_memory.sv
View File

@@ -73,7 +73,7 @@ taxi_axi_ram_if_rdwr #(
);
logic [7:0] mem [4][14*1024];
logic [7:0] mem [4][16*1024];
enum logic {CPU, EXT} sel, sel_next;

22
src/verilog6502_wrapper.sv
View File

@@ -1,11 +1,11 @@
// Wrapper around verilog-6502
// memory map:
// 0x0000-0x00FF Zero Page (Hard coded)
// 0x0100-0x01FF Stack (Hard coded)
// 0x0200-0xCFFF Internal Memory
// 0xE000-0xEFFF External AXI
// 0xF000-0xFFFF Processor IO
// 0x00000000-0x000000FF Zero Page (Hard coded)
// 0x00000100-0x000001FF Stack (Hard coded)
// 0x00000200-0x0000FFFF Internal Memory
// 0x00010000-0xFFFFEFFF External AXI
// 0xFFFFF000-0xFFFFFFFF Processor IO
module verilog6502_wrapper(
input clk,
@@ -59,7 +59,7 @@ taxi_apb_interconnect #(
logic cpu_clk;
logic cpu_reset;
logic [15:0] cpu_addr;
logic [31:0] cpu_addr;
logic [7:0] cpu_data_in;
logic [7:0] cpu_data_out;
@@ -83,14 +83,14 @@ logic mem_rd;
logic mem_we;
logic mem_rdy;
logic [15:0] ext_addr;
logic [31:0] ext_addr;
logic [7:0] ext_data_in;
logic [7:0] ext_data_out;
logic ext_rd;
logic ext_we;
logic ext_rdy;
logic [15:0] io_addr;
logic [11:0] io_addr;
logic [7:0] io_data_in;
logic [7:0] io_data_out;
logic io_rd;
@@ -173,13 +173,13 @@ verilog6502_external_memory u_external_memory (
.i_we (ext_we),
.o_rdy (ext_rdy),
.i_axi_base_addr (hwif_out.axi_base_address.val.value),
.m_axil_rd (m_axil_rd),
.m_axil_wr (m_axil_wr)
);
verilog6502_apb_adapter u_io_apb_adapter(
verilog6502_apb_adapter #(
.ADDR_WIDTH(12)
) u_io_apb_adapter(
.i_clk (cpu_clk),
.i_rst (rst),