bslathi19/verilog6502
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Add cc65 code

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Byron Lathi
2026-05-08 09:54:14 -07:00
parent 3c8df89769
commit c4d91a1994
11 changed files with 226 additions and 22 deletions
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13
sim/asm_source/memory.cfg Normal file
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@@ -0,0 +1,13 @@
MEMORY {
ZP: start = $0, size = $100;
RAM: start = $fffff000, size = $1000, file=%O;
}
SEGMENTS {
ZEROPAGE: load = ZP, type = zp;
CODE: load = RAM, type = ro;
RODATA: load = RAM, type = ro;
DATA: load = RAM, type = rw;
BSS: load = RAM, type = bss, define = yes;
VECTORS: load = RAM, type = ro, start = $FFFFFFF4;
}