Add indexed indirect

2026-04-27 21:59:30 -07:00
parent b31d7490b2
commit dfe27d4ec7
2 changed files with 99 additions and 12 deletions
--- a/sim/verilog6502_32bit_test.py
+++ b/sim/verilog6502_32bit_test.py
@@ -339,3 +339,67 @@ async def test_indirect(dut):
    ]

    await check_instruction_sequence(dut, expected_cpu_outputs)
+
+@cocotb.test
+async def test_indexed_indirect(dut):
+    cocotb.start_soon(Clock(dut.clk, CLK_PERIOD, unit="ns").start())
+    cocotb.start_soon(handle_memory(dut))
+
+    write_dword(0xfffffff4, 0x200)
+
+    # ldy #1
+    # lda ($04),y
+    # iny
+    # inc
+    # sta ($04),y
+    write_bytes(0x200, [0xa0, 0x02])
+    write_bytes(0x202, [0xb1, 0x04])
+    write_bytes(0x204, [0xc8])
+    write_bytes(0x205, [0x1a])
+    write_bytes(0x206, [0x91, 0x04])
+    write_byte(0x208, 0xcb)
+
+    write_dword(0x04, 0xabcdbeef)
+    write_dword(0xabcdbeef+2, 0xaa)
+
+    dut.RDY.value = Immediate(1)
+
+    dut.reset.value = Immediate(1)
+    for _ in range(10):
+        await RisingEdge(dut.clk)
+    dut.reset.value = 0
+
+    expected_cpu_outputs = [
+        None,   # ignore reset sequence
+        None,
+        None,
+        None,
+        None,
+        None,
+        None,
+        None,
+        None,
+        (0x00000200, False, None),            # ldy #0
+        (0x00000201, False, None),            # Immediate
+        (0x00000202, False, None),            # lda ($04),y
+        (0x00000203, False, None),            # ZP index
+        (0x00000004, False, None),            # zp addr 0
+        (0x00000005, False, None),            # zp addr 1
+        (0x00000006, False, None),            # zp addr 2
+        (0x00000007, False, None),            # zp addr 3
+        (0xabcdbef1, False, None),            # fetch data
+        (0x00000204, False, None),            # iny
+        (0x00000205, False, None),            # iny
+        (0x00000205, False, None),            # inc
+        (0x00000206, False, None),            # inc
+        (0x00000206, False, None),            # sta ($04),y
+        (0x00000207, False, None),            # ZP index
+        (0x00000004, False, None),            # zp addr 0
+        (0x00000005, False, None),            # zp addr 1
+        (0x00000006, False, None),            # zp addr 2
+        (0x00000007, False, None),            # zp addr 3
+        (0xabcdbef2, False, None),            # store takes extra cycle
+        (0xabcdbef2, True, 0xAB),             # write data
+    ]
+    
+    await check_instruction_sequence(dut, expected_cpu_outputs)