Files
verilog6502/sim/verilog6502_32bit.yaml
2026-04-26 08:53:59 -07:00

9 lines
173 B
YAML

tests:
- name: "cpu_65c02"
toplevel: "cpu_65c02"
modules:
- "verilog6502_32bit_test"
sources: "sources.list"
waves: True
defines:
SIM: "hi"