Byron Lathi 019b84f41d Get reset sequence to work

2026-04-26 19:28:39 -07:00

..

sub

Factor out verilog-6502 submodule

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sources.list

Factor out verilog-6502 submodule

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verilator.vlt

Create project

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verilog6502_32bit_test.py

Get reset sequence to work

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verilog6502_32bit.yaml

Add 32 bit BRK

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verilog6502_wrapper_tb.sv

Create project

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verilog6502_wrapper_test.py

Create project

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verilog6502_wrapper.yaml

Create project

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