bslathi19/verilog6502
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019b84f41d6ea775194eeeb250fbd0eb185c3779
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Byron Lathi 019b84f41d Get reset sequence to work
2026-04-26 19:28:39 -07:00
sim
Get reset sequence to work
2026-04-26 19:28:39 -07:00
src
Get reset sequence to work
2026-04-26 19:28:39 -07:00
.gitignore
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2026-04-18 18:50:18 -07:00
.gitmodules
Factor out verilog-6502 submodule
2026-04-18 18:55:05 -07:00
init_env.sh
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2026-04-18 18:50:18 -07:00
requirements.txt
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2026-04-18 18:50:18 -07:00
Description
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140 KiB
Languages
SystemVerilog 54.3%
Verilog 44.1%
Python 1.3%
Shell 0.3%