Byron Lathi 3c8df89769 Add branches

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sim

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src

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.gitignore

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.gitmodules

Factor out verilog-6502 submodule

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init_env.sh

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requirements.txt

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Description

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340 KiB

Languages

SystemVerilog 40.2%

Verilog 37.1%

Python 20.6%

Assembly 1.6%

Makefile 0.3%

Other 0.2%