Byron Lathi 6c6c3d295b Add design doc ...

but I didn't really read it

2026-05-24 20:09:02 -07:00

sim

Get it working more

2026-05-24 17:13:20 -07:00

src

Add design doc

2026-05-24 20:09:02 -07:00

.gitignore

32bit (#2)

2026-05-09 15:33:54 -07:00

.gitmodules

Factor out verilog-6502 submodule

2026-04-18 18:55:05 -07:00

init_env.sh

32bit (#2)

2026-05-09 15:33:54 -07:00

requirements.txt

Create project

2026-04-18 18:50:18 -07:00

Description

No description provided

340 KiB

Languages

SystemVerilog 40.2%

Verilog 37.1%

Python 20.6%

Assembly 1.6%

Makefile 0.3%

Other 0.2%