137 lines
4.4 KiB
Python
137 lines
4.4 KiB
Python
import cocotb
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from cocotb.handle import Immediate
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from cocotb.clock import Clock
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from cocotb.triggers import Timer, RisingEdge
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from collections import defaultdict
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CLK_PERIOD = 5
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memory = defaultdict(int)
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def write_dword(addr: int, data: int):
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memory[addr + 0] = (data >> 0) & 0xff
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memory[addr + 1] = (data >> 8) & 0xff
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memory[addr + 2] = (data >> 16) & 0xff
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memory[addr + 3] = (data >> 24) & 0xff
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def write_byte(addr: int, data: int):
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memory[addr] = data & 0xff
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def write_bytes(addr: int, data: bytes| list[int]):
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for i, val in enumerate(data):
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memory[addr + i] = int(val)
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async def handle_memory(dut):
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while True:
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await RisingEdge(dut.clk)
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addr = int(dut.AB.value)
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we = bool(dut.WE.value)
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dut.DI.value = memory[addr]
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if we:
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memory[addr] = int(dut.DO.value)
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@cocotb.test
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async def test_reset(dut):
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cocotb.start_soon(Clock(dut.clk, CLK_PERIOD, unit="ns").start())
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cocotb.start_soon(handle_memory(dut))
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write_dword(0xfffffff4, 0x12345678)
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dut.RDY.value = Immediate(1)
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dut.reset.value = Immediate(1)
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for _ in range(10):
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await RisingEdge(dut.clk)
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dut.reset.value = 0
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expected_cpu_outputs = [
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(0x00000100, True, (int(dut.PC.value) >> 24) & 0xff), # High addr
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(0x000001ff, True, (int(dut.PC.value) >> 16) & 0xff), # Mid high addr
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(0x000001fe, True, (int(dut.PC.value) >> 8) & 0xff), # Mid low addr
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(0x000001fd, True, (int(dut.PC.value) >> 0) & 0xff), # Low addr
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(0x000001fc, True, int(dut.P.value)), # Status
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(0xfffffff4, False, int(dut.regfile.value)), # read vector byte 0
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(0xfffffff5, False, int(dut.regfile.value)), # read vector byte 1
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(0xfffffff6, False, int(dut.regfile.value)), # read vector byte 2
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(0xfffffff7, False, int(dut.regfile.value)), # read vector byte 3
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(0x12345678, False, int(dut.regfile.value)), # Read first instruction
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(0x12345679, False, int(dut.regfile.value)), # Read second byte
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]
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for expected_output in expected_cpu_outputs:
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await RisingEdge(dut.clk)
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expected_addr, expected_we, expected_do = expected_output
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dut_addr = int(dut.AB.value)
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dut_we = bool(dut.WE.value)
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dut_do = int(dut.DO.value)
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assert dut_addr == expected_addr
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assert dut_we == expected_we
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assert dut_do == expected_do
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@cocotb.test
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async def test_absolute(dut):
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cocotb.start_soon(Clock(dut.clk, CLK_PERIOD, unit="ns").start())
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cocotb.start_soon(handle_memory(dut))
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write_dword(0xfffffff4, 0x200)
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# lda #$abcd1234
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# wai
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write_bytes(0x200, [0xad, 0x34, 0x12, 0xcd, 0xab])
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write_bytes(0x205, [0x8d, 0x53, 0x52, 0x51, 0x50])
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write_byte(0x20a, 0xcb)
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write_byte(0xabcd1234, 0x55)
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dut.RDY.value = Immediate(1)
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dut.reset.value = Immediate(1)
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for _ in range(10):
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await RisingEdge(dut.clk)
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dut.reset.value = 0
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expected_cpu_outputs = [
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None, # ignore reset sequence
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None,
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None,
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None,
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None,
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None,
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None,
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None,
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None,
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(0x00000200, False, None), # Read first instruction
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(0x00000201, False, None), # Read address byte 0
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(0x00000202, False, None), # Read address byte 1
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(0x00000203, False, None), # Read address byte 2
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(0x00000204, False, None), # Read address byte 3
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(0xabcd1234, False, None), # Read from absolute address
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(0x00000205, False, None), # Read second instruction
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(0x00000206, False, None), # Read address byte 0
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(0x00000207, False, None), # Read address byte 1
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(0x00000208, False, None), # Read address byte 2
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(0x00000209, False, None), # Read address byte 3
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(0x50515253, True, 0x55), # Write to absolute address
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]
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for expected_output in expected_cpu_outputs:
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await RisingEdge(dut.clk)
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if expected_output:
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expected_addr, expected_we, expected_do = expected_output
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dut_addr = int(dut.AB.value)
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dut_we = bool(dut.WE.value)
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dut_do = int(dut.DO.value)
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assert dut_addr == expected_addr
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assert dut_we == expected_we
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if dut_we:
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assert dut_do == expected_do
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