Byron Lathi 9476c6a0dd Add 32 bit BRK

2026-04-26 08:53:59 -07:00

sim

Add 32 bit BRK

2026-04-26 08:53:59 -07:00

src

Add 32 bit BRK

2026-04-26 08:53:59 -07:00

.gitignore

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2026-04-18 18:50:18 -07:00

.gitmodules

Factor out verilog-6502 submodule

2026-04-18 18:55:05 -07:00

init_env.sh

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2026-04-18 18:50:18 -07:00

requirements.txt

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2026-04-18 18:50:18 -07:00

Description

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140 KiB

Languages

SystemVerilog 54.3%

Verilog 44.1%

Python 1.3%

Shell 0.3%