bslathi19/verilog6502
1
0
Fork 0
Code Issues 1 Pull Requests Actions Packages Projects Releases Wiki Activity
9 Commits 2 Branches 0 Tags
aa8c4a64dffb4c783a5266c45281391801600246
Go to file
Clone
Open with VS Code Open with VSCodium Open with Intellij IDEA
Download ZIP Download TAR.GZ Download BUNDLE
Byron Lathi aa8c4a64df First shot at happy path
2026-05-22 23:54:33 -07:00
sim
Add cache arrays and test
2026-05-22 22:27:53 -07:00
src
First shot at happy path
2026-05-22 23:54:33 -07:00
.gitignore
…
.gitmodules
…
init_env.sh
…
requirements.txt
…
Description
No description provided
340 KiB
Languages
SystemVerilog 40.2%
Verilog 37.1%
Python 20.6%
Assembly 1.6%
Makefile 0.3%
Other 0.2%