Byron Lathi d1165bc9c9 Add jsr and rts

2026-04-30 21:27:59 -07:00

sim

Add jsr and rts

2026-04-30 21:27:59 -07:00

src

Add jsr and rts

2026-04-30 21:27:59 -07:00

.gitignore

Create project

2026-04-18 18:50:18 -07:00

.gitmodules

Factor out verilog-6502 submodule

2026-04-18 18:55:05 -07:00

init_env.sh

Create project

2026-04-18 18:50:18 -07:00

requirements.txt

Create project

2026-04-18 18:50:18 -07:00

Description

No description provided

294 KiB

Languages

SystemVerilog 40.2%

Verilog 37.1%

Python 20.6%

Assembly 1.6%

Makefile 0.3%

Other 0.2%