Byron Lathi d519943385 Add RTI

2026-04-30 22:24:31 -07:00

sim

Add RTI

2026-04-30 22:24:31 -07:00

src

Add RTI

2026-04-30 22:24:31 -07:00

.gitignore

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2026-04-18 18:50:18 -07:00

.gitmodules

Factor out verilog-6502 submodule

2026-04-18 18:55:05 -07:00

init_env.sh

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2026-04-18 18:50:18 -07:00

requirements.txt

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2026-04-18 18:50:18 -07:00

Description

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294 KiB

Languages

SystemVerilog 40.2%

Verilog 37.1%

Python 20.6%

Assembly 1.6%

Makefile 0.3%

Other 0.2%