bslathi19/verilog6502
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db61ca2d74a8a59386fd1e7600fa55f47b37091d
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Byron Lathi db61ca2d74 Create project
2026-04-18 18:50:18 -07:00
sim
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src
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.gitignore
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.gitmodules
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init_env.sh
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requirements.txt
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Description
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294 KiB
Languages
SystemVerilog 40.2%
Verilog 37.1%
Python 20.6%
Assembly 1.6%
Makefile 0.3%
Other 0.2%