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wireguard_fpga/Ti375C529_devkit/EfxSapphireHpSoc_slb.v
Byron Lathi 2f2727777b Start work on parser
2026-08-13 08:35:49 -07:00

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// =============================================================================
// Generated by efx_ipmgr
// Version: 2025.2.288.2.10
// IP Version: 1.22.0
// =============================================================================
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2025 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
`define IP_UUID _86b7e1c47b934a8a97a62bda8ee6a75d
`define IP_NAME_CONCAT(a,b) a``b
`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID)
module EfxSapphireHpSoc_slb
(
input io_peripheralClk,
input io_peripheralReset,
output io_asyncReset,
input io_gpio_sw_n,
input pll_peripheral_locked,
input pll_system_locked,
output jtagCtrl_capture,
output jtagCtrl_enable,
output jtagCtrl_reset,
output jtagCtrl_shift,
output jtagCtrl_tdi,
input jtagCtrl_tdo,
output jtagCtrl_update,
input ut_jtagCtrl_capture,
input ut_jtagCtrl_enable,
input ut_jtagCtrl_reset,
input ut_jtagCtrl_shift,
input ut_jtagCtrl_tdi,
output ut_jtagCtrl_tdo,
input ut_jtagCtrl_update,
input system_spi_0_io_data_0_read,
output system_spi_0_io_data_0_write,
output system_spi_0_io_data_0_writeEnable,
input system_spi_0_io_data_1_read,
output system_spi_0_io_data_1_write,
output system_spi_0_io_data_1_writeEnable,
input system_spi_0_io_data_2_read,
output system_spi_0_io_data_2_write,
output system_spi_0_io_data_2_writeEnable,
input system_spi_0_io_data_3_read,
output system_spi_0_io_data_3_write,
output system_spi_0_io_data_3_writeEnable,
output system_spi_0_io_sclk_write,
output [3:0] system_spi_0_io_ss,
input system_uart_0_io_rxd,
output system_uart_0_io_txd,
input cfg_done,
output cfg_start,
output cfg_sel,
output cfg_reset,
output axiAInterrupt,
input [31:0] axiA_awaddr,
input [7:0] axiA_awlen,
input [2:0] axiA_awsize,
input [1:0] axiA_awburst,
input axiA_awlock,
input [3:0] axiA_awcache,
input [2:0] axiA_awprot,
input [3:0] axiA_awqos,
input [3:0] axiA_awregion,
input axiA_awvalid,
output axiA_awready,
input [31:0] axiA_wdata,
input [3:0] axiA_wstrb,
input axiA_wvalid,
input axiA_wlast,
output axiA_wready,
output [1:0] axiA_bresp,
output axiA_bvalid,
input axiA_bready,
input [31:0] axiA_araddr,
input [7:0] axiA_arlen,
input [2:0] axiA_arsize,
input [1:0] axiA_arburst,
input axiA_arlock,
input [3:0] axiA_arcache,
input [2:0] axiA_arprot,
input [3:0] axiA_arqos,
input [3:0] axiA_arregion,
input axiA_arvalid,
output axiA_arready,
output [31:0] axiA_rdata,
output [1:0] axiA_rresp,
output axiA_rlast,
output axiA_rvalid,
input axiA_rready,
output userInterruptA,
output userInterruptB
);
`IP_MODULE_NAME(Axi4Peripheral_wrapper)
#(
.PERI_FREQ (250)
)
u_Axi4Peripheral_wrapper
(
.io_peripheralClk ( io_peripheralClk ),
.io_peripheralReset ( io_peripheralReset ),
.io_asyncReset ( io_asyncReset ),
.io_gpio_sw_n ( io_gpio_sw_n ),
.pll_peripheral_locked ( pll_peripheral_locked ),
.pll_system_locked ( pll_system_locked ),
.jtagCtrl_capture ( jtagCtrl_capture ),
.jtagCtrl_enable ( jtagCtrl_enable ),
.jtagCtrl_reset ( jtagCtrl_reset ),
.jtagCtrl_shift ( jtagCtrl_shift ),
.jtagCtrl_tdi ( jtagCtrl_tdi ),
.jtagCtrl_tdo ( jtagCtrl_tdo ),
.jtagCtrl_update ( jtagCtrl_update ),
.ut_jtagCtrl_capture ( ut_jtagCtrl_capture ),
.ut_jtagCtrl_enable ( ut_jtagCtrl_enable ),
.ut_jtagCtrl_reset ( ut_jtagCtrl_reset ),
.ut_jtagCtrl_shift ( ut_jtagCtrl_shift ),
.ut_jtagCtrl_tdi ( ut_jtagCtrl_tdi ),
.ut_jtagCtrl_tdo ( ut_jtagCtrl_tdo ),
.ut_jtagCtrl_update ( ut_jtagCtrl_update ),
.system_spi_0_io_data_0_read ( system_spi_0_io_data_0_read ),
.system_spi_0_io_data_0_write ( system_spi_0_io_data_0_write ),
.system_spi_0_io_data_0_writeEnable ( system_spi_0_io_data_0_writeEnable ),
.system_spi_0_io_data_1_read ( system_spi_0_io_data_1_read ),
.system_spi_0_io_data_1_write ( system_spi_0_io_data_1_write ),
.system_spi_0_io_data_1_writeEnable ( system_spi_0_io_data_1_writeEnable ),
.system_spi_0_io_data_2_read ( system_spi_0_io_data_2_read ),
.system_spi_0_io_data_2_write ( system_spi_0_io_data_2_write ),
.system_spi_0_io_data_2_writeEnable ( system_spi_0_io_data_2_writeEnable ),
.system_spi_0_io_data_3_read ( system_spi_0_io_data_3_read ),
.system_spi_0_io_data_3_write ( system_spi_0_io_data_3_write ),
.system_spi_0_io_data_3_writeEnable ( system_spi_0_io_data_3_writeEnable ),
.system_spi_0_io_sclk_write ( system_spi_0_io_sclk_write ),
.system_spi_0_io_ss ( system_spi_0_io_ss ),
.system_uart_0_io_rxd ( system_uart_0_io_rxd ),
.system_uart_0_io_txd ( system_uart_0_io_txd ),
.cfg_done ( cfg_done ),
.cfg_start ( cfg_start ),
.cfg_sel ( cfg_sel ),
.cfg_reset ( cfg_reset ),
.axiAInterrupt ( axiAInterrupt ),
.axiA_awaddr ( axiA_awaddr ),
.axiA_awlen ( axiA_awlen ),
.axiA_awsize ( axiA_awsize ),
.axiA_awburst ( axiA_awburst ),
.axiA_awlock ( axiA_awlock ),
.axiA_awcache ( axiA_awcache ),
.axiA_awprot ( axiA_awprot ),
.axiA_awqos ( axiA_awqos ),
.axiA_awregion ( axiA_awregion ),
.axiA_awvalid ( axiA_awvalid ),
.axiA_awready ( axiA_awready ),
.axiA_wdata ( axiA_wdata ),
.axiA_wstrb ( axiA_wstrb ),
.axiA_wvalid ( axiA_wvalid ),
.axiA_wlast ( axiA_wlast ),
.axiA_wready ( axiA_wready ),
.axiA_bresp ( axiA_bresp ),
.axiA_bvalid ( axiA_bvalid ),
.axiA_bready ( axiA_bready ),
.axiA_araddr ( axiA_araddr ),
.axiA_arlen ( axiA_arlen ),
.axiA_arsize ( axiA_arsize ),
.axiA_arburst ( axiA_arburst ),
.axiA_arlock ( axiA_arlock ),
.axiA_arcache ( axiA_arcache ),
.axiA_arprot ( axiA_arprot ),
.axiA_arqos ( axiA_arqos ),
.axiA_arregion ( axiA_arregion ),
.axiA_arvalid ( axiA_arvalid ),
.axiA_arready ( axiA_arready ),
.axiA_rdata ( axiA_rdata ),
.axiA_rresp ( axiA_rresp ),
.axiA_rlast ( axiA_rlast ),
.axiA_rvalid ( axiA_rvalid ),
.axiA_rready ( axiA_rready ),
.userInterruptA ( userInterruptA ),
.userInterruptB ( userInterruptB )
);
endmodule
module `IP_MODULE_NAME(Axi4Peripheral_wrapper) #(
parameter PERI_FREQ=250
)(
output system_spi_0_io_sclk_write,
output system_spi_0_io_data_0_writeEnable,
input system_spi_0_io_data_0_read,
output system_spi_0_io_data_0_write,
output system_spi_0_io_data_1_writeEnable,
input system_spi_0_io_data_1_read,
output system_spi_0_io_data_1_write,
output system_spi_0_io_data_2_writeEnable,
input system_spi_0_io_data_2_read,
output system_spi_0_io_data_2_write,
output system_spi_0_io_data_3_writeEnable,
input system_spi_0_io_data_3_read,
output system_spi_0_io_data_3_write,
output [3:0] system_spi_0_io_ss,
output userInterruptB,
output jtagCtrl_tdi,
input jtagCtrl_tdo,
output jtagCtrl_enable,
output jtagCtrl_capture,
output jtagCtrl_shift,
output jtagCtrl_update,
output jtagCtrl_reset,
input ut_jtagCtrl_tdi,
output ut_jtagCtrl_tdo,
input ut_jtagCtrl_enable,
input ut_jtagCtrl_capture,
input ut_jtagCtrl_shift,
input ut_jtagCtrl_update,
input ut_jtagCtrl_reset,
output userInterruptA,
output system_uart_0_io_txd,
input system_uart_0_io_rxd,
input [31:0] axiA_awaddr,
input [7:0] axiA_awlen,
input [2:0] axiA_awsize,
input [1:0] axiA_awburst,
input axiA_awlock,
input [3:0] axiA_awcache,
input [2:0] axiA_awprot,
input [3:0] axiA_awqos,
input [3:0] axiA_awregion,
input axiA_awvalid,
output axiA_awready,
input [31:0] axiA_wdata,
input [3:0] axiA_wstrb,
input axiA_wvalid,
input axiA_wlast,
output axiA_wready,
output [1:0] axiA_bresp,
output axiA_bvalid,
input axiA_bready,
input [31:0] axiA_araddr,
input [7:0] axiA_arlen,
input [2:0] axiA_arsize,
input [1:0] axiA_arburst,
input axiA_arlock,
input [3:0] axiA_arcache,
input [2:0] axiA_arprot,
input [3:0] axiA_arqos,
input [3:0] axiA_arregion,
input axiA_arvalid,
output axiA_arready,
output [31:0] axiA_rdata,
output [1:0] axiA_rresp,
output axiA_rlast,
output axiA_rvalid,
input axiA_rready,
output axiAInterrupt,
input cfg_done,
output cfg_start,
output cfg_sel,
output cfg_reset,
input io_peripheralClk,
input io_peripheralReset,
output io_asyncReset,
input io_gpio_sw_n,
input pll_peripheral_locked,
input pll_system_locked
);
wire flag_ok;
wire system_spi_0_io_interrupt;
wire system_uart_0_io_interrupt;
`IP_MODULE_NAME(lppdr4_init) u_lppdr4_init (
.io_peripheralClk (io_peripheralClk),
.io_peripheralReset (io_peripheralReset),
.io_gpio_sw_n (io_gpio_sw_n),
.flag_ok (flag_ok),
.cfg_done (cfg_done),
.cfg_start (cfg_start),
.cfg_sel (cfg_sel),
.cfg_reset (cfg_reset)
);
assign io_asyncReset = ~(io_gpio_sw_n &
pll_peripheral_locked &
pll_system_locked &
flag_ok);
assign userInterruptA = system_uart_0_io_interrupt;
assign userInterruptB = system_spi_0_io_interrupt;
assign jtagCtrl_capture = ut_jtagCtrl_capture;
assign jtagCtrl_enable = ut_jtagCtrl_enable;
assign jtagCtrl_reset = ut_jtagCtrl_reset;
assign jtagCtrl_shift = ut_jtagCtrl_shift;
assign jtagCtrl_tdi = ut_jtagCtrl_tdi;
assign jtagCtrl_update = ut_jtagCtrl_update;
assign ut_jtagCtrl_tdo = jtagCtrl_tdo;
//axi4 bridge to various I/O
Axi4PeripheralTop_86b7e1c47b934a8a97a62bda8ee6a75d u_Axi4PeripheralTop(
.system_spi_0_io_interrupt(system_spi_0_io_interrupt),
.system_spi_0_io_sclk_write(system_spi_0_io_sclk_write),
.system_spi_0_io_data_0_writeEnable(system_spi_0_io_data_0_writeEnable),
.system_spi_0_io_data_0_read(system_spi_0_io_data_0_read),
.system_spi_0_io_data_0_write(system_spi_0_io_data_0_write),
.system_spi_0_io_data_1_writeEnable(system_spi_0_io_data_1_writeEnable),
.system_spi_0_io_data_1_read(system_spi_0_io_data_1_read),
.system_spi_0_io_data_1_write(system_spi_0_io_data_1_write),
.system_spi_0_io_data_2_writeEnable(system_spi_0_io_data_2_writeEnable),
.system_spi_0_io_data_2_read(system_spi_0_io_data_2_read),
.system_spi_0_io_data_2_write(system_spi_0_io_data_2_write),
.system_spi_0_io_data_3_writeEnable(system_spi_0_io_data_3_writeEnable),
.system_spi_0_io_data_3_read(system_spi_0_io_data_3_read),
.system_spi_0_io_data_3_write(system_spi_0_io_data_3_write),
.system_spi_0_io_ss(system_spi_0_io_ss),
.system_uart_0_io_interrupt(system_uart_0_io_interrupt),
.system_uart_0_io_txd(system_uart_0_io_txd),
.system_uart_0_io_rxd(system_uart_0_io_rxd),
.axi_awvalid(axiA_awvalid),
.axi_awready(axiA_awready),
.axi_awaddr(axiA_awaddr[23:0]),
.axi_awlen(axiA_awlen),
.axi_awsize(axiA_awsize),
.axi_awcache(axiA_awcache),
.axi_awprot(axiA_awprot),
.axi_wvalid(axiA_wvalid),
.axi_wready(axiA_wready),
.axi_wdata(axiA_wdata),
.axi_wstrb(axiA_wstrb),
.axi_wlast(axiA_wlast),
.axi_bvalid(axiA_bvalid),
.axi_bready(axiA_bready),
.axi_bresp(axiA_bresp),
.axi_arvalid(axiA_arvalid),
.axi_arready(axiA_arready),
.axi_araddr(axiA_araddr[23:0]),
.axi_arlen(axiA_arlen),
.axi_arsize(axiA_arsize),
.axi_arcache(axiA_arcache),
.axi_arprot(axiA_arprot),
.axi_rvalid(axiA_rvalid),
.axi_rready(axiA_rready),
.axi_rdata(axiA_rdata),
.axi_rresp(axiA_rresp),
.axi_rlast(axiA_rlast),
.clk(io_peripheralClk),
.reset(io_peripheralReset)
);
assign axiAInterrupt = 1'b0;
endmodule
module `IP_MODULE_NAME(lppdr4_init) (
input io_peripheralClk,
input io_peripheralReset,
input io_gpio_sw_n,
output reg flag_ok,
input cfg_done,
output cfg_start,
output cfg_sel,
output cfg_reset
);
localparam [1:0] IDLE = 2'b00,
CFG_START = 2'b01,
CFG_DONE = 2'b11;
reg [1:0] cfg_st,
cfg_next;
reg [7:0] cfg_count;
wire cfg_ok;
reg [1:0] buf_reset;
wire dmReset;
always@(posedge io_peripheralClk)
begin
buf_reset[1] <= io_peripheralReset;
buf_reset[0] <= buf_reset[1];
end
assign dmReset = (~buf_reset[0] & buf_reset[1]);
always@(posedge io_peripheralClk or negedge io_gpio_sw_n)
begin
if(!io_gpio_sw_n)
flag_ok <= 1'b0;
else
begin
if(cfg_st == CFG_DONE)
flag_ok <= 1'b1;
else
flag_ok <= flag_ok;
end
end
always@(posedge io_peripheralClk or negedge io_gpio_sw_n)
begin
if(!io_gpio_sw_n || dmReset)
cfg_st <= IDLE;
else
cfg_st <= cfg_next;
end
always@(*)
begin
cfg_next = cfg_st;
case(cfg_st)
IDLE:
begin
if(cfg_count == 'hff)
cfg_next = CFG_START;
else
cfg_next = IDLE;
end
CFG_START:
begin
if(cfg_done)
cfg_next = CFG_DONE;
else
cfg_next = CFG_START;
end
CFG_DONE:
cfg_next = CFG_DONE;
default:
cfg_next = IDLE;
endcase
end
assign cfg_start = (cfg_st != IDLE);
assign cfg_ok = (cfg_st == CFG_DONE);
assign cfg_reset = (cfg_st == IDLE);
assign cfg_sel = 1'b0;
always@(posedge io_peripheralClk)
begin
if(cfg_st == IDLE)
cfg_count <= cfg_count + 1'b1;
else
cfg_count <= 'h0;
end
endmodule
// Generator : SpinalHDL dev git head : a69f4b9a329be784802c37cd8038b7dc9aec3094
// Component : Axi4PeripheralTop_86b7e1c47b934a8a97a62bda8ee6a75d
`timescale 1ns/1ps
module Axi4PeripheralTop_86b7e1c47b934a8a97a62bda8ee6a75d (
input wire axi_awvalid,
output wire axi_awready,
input wire [23:0] axi_awaddr,
input wire [7:0] axi_awlen,
input wire [2:0] axi_awsize,
input wire [3:0] axi_awcache,
input wire [2:0] axi_awprot,
input wire axi_wvalid,
output wire axi_wready,
input wire [31:0] axi_wdata,
input wire [3:0] axi_wstrb,
input wire axi_wlast,
output wire axi_bvalid,
input wire axi_bready,
output wire [1:0] axi_bresp,
input wire axi_arvalid,
output wire axi_arready,
input wire [23:0] axi_araddr,
input wire [7:0] axi_arlen,
input wire [2:0] axi_arsize,
input wire [3:0] axi_arcache,
input wire [2:0] axi_arprot,
output wire axi_rvalid,
input wire axi_rready,
output wire [31:0] axi_rdata,
output wire [1:0] axi_rresp,
output wire axi_rlast,
output wire system_uart_0_io_txd,
input wire system_uart_0_io_rxd,
output wire system_uart_0_io_interrupt,
output wire system_spi_0_io_interrupt,
output wire [0:0] system_spi_0_io_sclk_write,
output wire system_spi_0_io_data_0_writeEnable,
input wire [0:0] system_spi_0_io_data_0_read,
output wire [0:0] system_spi_0_io_data_0_write,
output wire system_spi_0_io_data_1_writeEnable,
input wire [0:0] system_spi_0_io_data_1_read,
output wire [0:0] system_spi_0_io_data_1_write,
output wire system_spi_0_io_data_2_writeEnable,
input wire [0:0] system_spi_0_io_data_2_read,
output wire [0:0] system_spi_0_io_data_2_write,
output wire system_spi_0_io_data_3_writeEnable,
input wire [0:0] system_spi_0_io_data_3_read,
output wire [0:0] system_spi_0_io_data_3_write,
output wire [3:0] system_spi_0_io_ss,
input wire clk,
input wire reset
);
wire streamArbiter_io_inputs_0_ready;
wire streamArbiter_io_inputs_1_ready;
wire streamArbiter_io_output_valid;
wire [23:0] streamArbiter_io_output_payload_addr;
wire [7:0] streamArbiter_io_output_payload_len;
wire [2:0] streamArbiter_io_output_payload_size;
wire [3:0] streamArbiter_io_output_payload_cache;
wire [2:0] streamArbiter_io_output_payload_prot;
wire [0:0] streamArbiter_io_chosen;
wire [1:0] streamArbiter_io_chosenOH;
wire axiToBmb_io_axi_arw_ready;
wire axiToBmb_io_axi_w_ready;
wire axiToBmb_io_axi_b_valid;
wire [1:0] axiToBmb_io_axi_b_payload_resp;
wire axiToBmb_io_axi_r_valid;
wire [31:0] axiToBmb_io_axi_r_payload_data;
wire [1:0] axiToBmb_io_axi_r_payload_resp;
wire axiToBmb_io_axi_r_payload_last;
wire axiToBmb_io_bmb_cmd_valid;
wire axiToBmb_io_bmb_cmd_payload_last;
wire [0:0] axiToBmb_io_bmb_cmd_payload_fragment_source;
wire [0:0] axiToBmb_io_bmb_cmd_payload_fragment_opcode;
wire [23:0] axiToBmb_io_bmb_cmd_payload_fragment_address;
wire [9:0] axiToBmb_io_bmb_cmd_payload_fragment_length;
wire [31:0] axiToBmb_io_bmb_cmd_payload_fragment_data;
wire [3:0] axiToBmb_io_bmb_cmd_payload_fragment_mask;
wire axiToBmb_io_bmb_rsp_ready;
wire bmbHandle_decoder_io_input_cmd_ready;
wire bmbHandle_decoder_io_input_rsp_valid;
wire bmbHandle_decoder_io_input_rsp_payload_last;
wire [0:0] bmbHandle_decoder_io_input_rsp_payload_fragment_source;
wire [0:0] bmbHandle_decoder_io_input_rsp_payload_fragment_opcode;
wire [31:0] bmbHandle_decoder_io_input_rsp_payload_fragment_data;
wire bmbHandle_decoder_io_outputs_0_cmd_valid;
wire bmbHandle_decoder_io_outputs_0_cmd_payload_last;
wire [0:0] bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_source;
wire [0:0] bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_opcode;
wire [23:0] bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_address;
wire [9:0] bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_length;
wire [31:0] bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_data;
wire [3:0] bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_mask;
wire bmbHandle_decoder_io_outputs_0_rsp_ready;
wire bmbHandle_unburstify_io_input_cmd_ready;
wire bmbHandle_unburstify_io_input_rsp_valid;
wire bmbHandle_unburstify_io_input_rsp_payload_last;
wire [0:0] bmbHandle_unburstify_io_input_rsp_payload_fragment_source;
wire [0:0] bmbHandle_unburstify_io_input_rsp_payload_fragment_opcode;
wire [31:0] bmbHandle_unburstify_io_input_rsp_payload_fragment_data;
wire bmbHandle_unburstify_io_output_cmd_valid;
wire bmbHandle_unburstify_io_output_cmd_payload_last;
wire [0:0] bmbHandle_unburstify_io_output_cmd_payload_fragment_opcode;
wire [23:0] bmbHandle_unburstify_io_output_cmd_payload_fragment_address;
wire [1:0] bmbHandle_unburstify_io_output_cmd_payload_fragment_length;
wire [31:0] bmbHandle_unburstify_io_output_cmd_payload_fragment_data;
wire [3:0] bmbHandle_unburstify_io_output_cmd_payload_fragment_mask;
wire [2:0] bmbHandle_unburstify_io_output_cmd_payload_fragment_context;
wire bmbHandle_unburstify_io_output_rsp_ready;
wire bmbPeripheral_bmb_decoder_io_input_cmd_ready;
wire bmbPeripheral_bmb_decoder_io_input_rsp_valid;
wire bmbPeripheral_bmb_decoder_io_input_rsp_payload_last;
wire [0:0] bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_opcode;
wire [31:0] bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_data;
wire [2:0] bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_context;
wire bmbPeripheral_bmb_decoder_io_outputs_0_cmd_valid;
wire bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_last;
wire [0:0] bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode;
wire [23:0] bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_address;
wire [1:0] bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_length;
wire [31:0] bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_data;
wire [3:0] bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_mask;
wire [2:0] bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_context;
wire bmbPeripheral_bmb_decoder_io_outputs_0_rsp_ready;
wire bmbPeripheral_bmb_decoder_io_outputs_1_cmd_valid;
wire bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_last;
wire [0:0] bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode;
wire [23:0] bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_address;
wire [1:0] bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_length;
wire [31:0] bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_data;
wire [3:0] bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_mask;
wire [2:0] bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_context;
wire bmbPeripheral_bmb_decoder_io_outputs_1_rsp_ready;
wire system_uart_0_io_logic_io_bus_cmd_ready;
wire system_uart_0_io_logic_io_bus_rsp_valid;
wire system_uart_0_io_logic_io_bus_rsp_payload_last;
wire [0:0] system_uart_0_io_logic_io_bus_rsp_payload_fragment_opcode;
wire [31:0] system_uart_0_io_logic_io_bus_rsp_payload_fragment_data;
wire [2:0] system_uart_0_io_logic_io_bus_rsp_payload_fragment_context;
wire system_uart_0_io_logic_io_uart_txd;
wire system_uart_0_io_logic_system_uart_0_io_interrupt_source;
wire system_spi_0_io_logic_io_ctrl_cmd_ready;
wire system_spi_0_io_logic_io_ctrl_rsp_valid;
wire system_spi_0_io_logic_io_ctrl_rsp_payload_last;
wire [0:0] system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_opcode;
wire [31:0] system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_data;
wire [2:0] system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_context;
wire [0:0] system_spi_0_io_logic_io_spi_sclk_write;
wire [3:0] system_spi_0_io_logic_io_spi_ss;
wire [0:0] system_spi_0_io_logic_io_spi_data_0_write;
wire system_spi_0_io_logic_io_spi_data_0_writeEnable;
wire [0:0] system_spi_0_io_logic_io_spi_data_1_write;
wire system_spi_0_io_logic_io_spi_data_1_writeEnable;
wire [0:0] system_spi_0_io_logic_io_spi_data_2_write;
wire system_spi_0_io_logic_io_spi_data_2_writeEnable;
wire [0:0] system_spi_0_io_logic_io_spi_data_3_write;
wire system_spi_0_io_logic_io_spi_data_3_writeEnable;
wire system_spi_0_io_logic_system_spi_0_io_interrupt_source;
wire _zz_axiShared_b_ready;
wire _zz_axiShared_r_ready;
wire axi_aw_halfPipe_valid;
wire axi_aw_halfPipe_ready;
wire [23:0] axi_aw_halfPipe_payload_addr;
wire [7:0] axi_aw_halfPipe_payload_len;
wire [2:0] axi_aw_halfPipe_payload_size;
wire [3:0] axi_aw_halfPipe_payload_cache;
wire [2:0] axi_aw_halfPipe_payload_prot;
reg axi_aw_rValid;
wire axi_aw_halfPipe_fire;
reg [23:0] axi_aw_rData_addr;
reg [7:0] axi_aw_rData_len;
reg [2:0] axi_aw_rData_size;
reg [3:0] axi_aw_rData_cache;
reg [2:0] axi_aw_rData_prot;
wire axi_w_halfPipe_valid;
wire axi_w_halfPipe_ready;
wire [31:0] axi_w_halfPipe_payload_data;
wire [3:0] axi_w_halfPipe_payload_strb;
wire axi_w_halfPipe_payload_last;
reg axi_w_rValid;
wire axi_w_halfPipe_fire;
reg [31:0] axi_w_rData_data;
reg [3:0] axi_w_rData_strb;
reg axi_w_rData_last;
wire _zz_axi_bvalid;
reg _zz_axi_bvalid_1;
reg [1:0] _zz_axi_bresp;
wire axi_ar_halfPipe_valid;
wire axi_ar_halfPipe_ready;
wire [23:0] axi_ar_halfPipe_payload_addr;
wire [7:0] axi_ar_halfPipe_payload_len;
wire [2:0] axi_ar_halfPipe_payload_size;
wire [3:0] axi_ar_halfPipe_payload_cache;
wire [2:0] axi_ar_halfPipe_payload_prot;
reg axi_ar_rValid;
wire axi_ar_halfPipe_fire;
reg [23:0] axi_ar_rData_addr;
reg [7:0] axi_ar_rData_len;
reg [2:0] axi_ar_rData_size;
reg [3:0] axi_ar_rData_cache;
reg [2:0] axi_ar_rData_prot;
wire _zz_axi_rvalid;
reg _zz_axi_rvalid_1;
reg [31:0] _zz_axi_rdata;
reg [1:0] _zz_axi_rresp;
reg _zz_axi_rlast;
wire axiShared_arw_valid;
wire axiShared_arw_ready;
wire [23:0] axiShared_arw_payload_addr;
wire [7:0] axiShared_arw_payload_len;
wire [2:0] axiShared_arw_payload_size;
wire [3:0] axiShared_arw_payload_cache;
wire [2:0] axiShared_arw_payload_prot;
wire axiShared_arw_payload_write;
wire axiShared_w_valid;
wire axiShared_w_ready;
wire [31:0] axiShared_w_payload_data;
wire [3:0] axiShared_w_payload_strb;
wire axiShared_w_payload_last;
wire axiShared_b_valid;
wire axiShared_b_ready;
wire [1:0] axiShared_b_payload_resp;
wire axiShared_r_valid;
wire axiShared_r_ready;
wire [31:0] axiShared_r_payload_data;
wire [1:0] axiShared_r_payload_resp;
wire axiShared_r_payload_last;
wire bmbPeripheral_bmb_cmd_valid;
wire bmbPeripheral_bmb_cmd_ready;
wire bmbPeripheral_bmb_cmd_payload_last;
wire [0:0] bmbPeripheral_bmb_cmd_payload_fragment_opcode;
wire [23:0] bmbPeripheral_bmb_cmd_payload_fragment_address;
wire [1:0] bmbPeripheral_bmb_cmd_payload_fragment_length;
wire [31:0] bmbPeripheral_bmb_cmd_payload_fragment_data;
wire [3:0] bmbPeripheral_bmb_cmd_payload_fragment_mask;
wire [2:0] bmbPeripheral_bmb_cmd_payload_fragment_context;
wire bmbPeripheral_bmb_rsp_valid;
wire bmbPeripheral_bmb_rsp_ready;
wire bmbPeripheral_bmb_rsp_payload_last;
wire [0:0] bmbPeripheral_bmb_rsp_payload_fragment_opcode;
wire [31:0] bmbPeripheral_bmb_rsp_payload_fragment_data;
wire [2:0] bmbPeripheral_bmb_rsp_payload_fragment_context;
wire bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid;
wire bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready;
wire bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last;
wire [0:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode;
wire [23:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address;
wire [1:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length;
wire [31:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data;
wire [3:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask;
wire [2:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context;
wire bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid;
wire bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready;
wire bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last;
wire [0:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode;
wire [31:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data;
wire [2:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context;
wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid;
wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready;
wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last;
wire [0:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode;
wire [5:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address;
wire [1:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length;
wire [31:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data;
wire [2:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context;
wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid;
wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready;
wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last;
wire [0:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode;
wire [31:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data;
wire [2:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context;
wire _zz_io_bus_rsp_ready;
wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid;
wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready;
wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last;
wire [0:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode;
wire [5:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address;
wire [1:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length;
wire [31:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data;
wire [2:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context;
reg system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid;
wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire;
reg system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last;
reg [0:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode;
reg [5:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address;
reg [1:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length;
reg [31:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data;
reg [2:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context;
wire _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid;
reg _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1;
reg _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last;
reg [0:0] _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode;
reg [31:0] _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data;
reg [2:0] _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context;
wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid;
wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready;
wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last;
wire [0:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode;
wire [11:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address;
wire [1:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length;
wire [31:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data;
wire [2:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context;
wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid;
wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready;
wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last;
wire [0:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode;
wire [31:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data;
wire [2:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context;
wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid;
wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready;
wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last;
wire [0:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode;
wire [11:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address;
wire [1:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length;
wire [31:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data;
wire [2:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context;
reg system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid;
wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire;
reg system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last;
reg [0:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode;
reg [11:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address;
reg [1:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length;
reg [31:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data;
reg [2:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context;
wire bmbPeripheral_bmb_withoutMask_cmd_valid;
wire bmbPeripheral_bmb_withoutMask_cmd_ready;
wire bmbPeripheral_bmb_withoutMask_cmd_payload_last;
wire [0:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode;
wire [23:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address;
wire [1:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length;
wire [31:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data;
wire [2:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context;
wire bmbPeripheral_bmb_withoutMask_rsp_valid;
wire bmbPeripheral_bmb_withoutMask_rsp_ready;
wire bmbPeripheral_bmb_withoutMask_rsp_payload_last;
wire [0:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode;
wire [31:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data;
wire [2:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context;
wire bmbPeripheral_bmb_withoutMask_cmd_valid_1;
wire bmbPeripheral_bmb_withoutMask_cmd_ready_1;
wire bmbPeripheral_bmb_withoutMask_cmd_payload_last_1;
wire [0:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_1;
wire [23:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_1;
wire [1:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_1;
wire [31:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_1;
wire [2:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_1;
wire bmbPeripheral_bmb_withoutMask_rsp_valid_1;
wire bmbPeripheral_bmb_withoutMask_rsp_ready_1;
wire bmbPeripheral_bmb_withoutMask_rsp_payload_last_1;
wire [0:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_1;
wire [31:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_1;
wire [2:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_1;
Axi4PeripheralStreamArbiter_86b7e1c47b934a8a97a62bda8ee6a75d streamArbiter (
.io_inputs_0_valid (axi_ar_halfPipe_valid ), //i
.io_inputs_0_ready (streamArbiter_io_inputs_0_ready ), //o
.io_inputs_0_payload_addr (axi_ar_halfPipe_payload_addr[23:0] ), //i
.io_inputs_0_payload_len (axi_ar_halfPipe_payload_len[7:0] ), //i
.io_inputs_0_payload_size (axi_ar_halfPipe_payload_size[2:0] ), //i
.io_inputs_0_payload_cache (axi_ar_halfPipe_payload_cache[3:0] ), //i
.io_inputs_0_payload_prot (axi_ar_halfPipe_payload_prot[2:0] ), //i
.io_inputs_1_valid (axi_aw_halfPipe_valid ), //i
.io_inputs_1_ready (streamArbiter_io_inputs_1_ready ), //o
.io_inputs_1_payload_addr (axi_aw_halfPipe_payload_addr[23:0] ), //i
.io_inputs_1_payload_len (axi_aw_halfPipe_payload_len[7:0] ), //i
.io_inputs_1_payload_size (axi_aw_halfPipe_payload_size[2:0] ), //i
.io_inputs_1_payload_cache (axi_aw_halfPipe_payload_cache[3:0] ), //i
.io_inputs_1_payload_prot (axi_aw_halfPipe_payload_prot[2:0] ), //i
.io_output_valid (streamArbiter_io_output_valid ), //o
.io_output_ready (axiShared_arw_ready ), //i
.io_output_payload_addr (streamArbiter_io_output_payload_addr[23:0]), //o
.io_output_payload_len (streamArbiter_io_output_payload_len[7:0] ), //o
.io_output_payload_size (streamArbiter_io_output_payload_size[2:0] ), //o
.io_output_payload_cache (streamArbiter_io_output_payload_cache[3:0]), //o
.io_output_payload_prot (streamArbiter_io_output_payload_prot[2:0] ), //o
.io_chosen (streamArbiter_io_chosen ), //o
.io_chosenOH (streamArbiter_io_chosenOH[1:0] ), //o
.clk (clk ), //i
.reset (reset ) //i
);
Axi4PeripheralAxi4SharedToBmb_86b7e1c47b934a8a97a62bda8ee6a75d axiToBmb (
.io_axi_arw_valid (axiShared_arw_valid ), //i
.io_axi_arw_ready (axiToBmb_io_axi_arw_ready ), //o
.io_axi_arw_payload_addr (axiShared_arw_payload_addr[23:0] ), //i
.io_axi_arw_payload_len (axiShared_arw_payload_len[7:0] ), //i
.io_axi_arw_payload_size (axiShared_arw_payload_size[2:0] ), //i
.io_axi_arw_payload_cache (axiShared_arw_payload_cache[3:0] ), //i
.io_axi_arw_payload_prot (axiShared_arw_payload_prot[2:0] ), //i
.io_axi_arw_payload_write (axiShared_arw_payload_write ), //i
.io_axi_w_valid (axiShared_w_valid ), //i
.io_axi_w_ready (axiToBmb_io_axi_w_ready ), //o
.io_axi_w_payload_data (axiShared_w_payload_data[31:0] ), //i
.io_axi_w_payload_strb (axiShared_w_payload_strb[3:0] ), //i
.io_axi_w_payload_last (axiShared_w_payload_last ), //i
.io_axi_b_valid (axiToBmb_io_axi_b_valid ), //o
.io_axi_b_ready (axiShared_b_ready ), //i
.io_axi_b_payload_resp (axiToBmb_io_axi_b_payload_resp[1:0] ), //o
.io_axi_r_valid (axiToBmb_io_axi_r_valid ), //o
.io_axi_r_ready (axiShared_r_ready ), //i
.io_axi_r_payload_data (axiToBmb_io_axi_r_payload_data[31:0] ), //o
.io_axi_r_payload_resp (axiToBmb_io_axi_r_payload_resp[1:0] ), //o
.io_axi_r_payload_last (axiToBmb_io_axi_r_payload_last ), //o
.io_bmb_cmd_valid (axiToBmb_io_bmb_cmd_valid ), //o
.io_bmb_cmd_ready (bmbHandle_decoder_io_input_cmd_ready ), //i
.io_bmb_cmd_payload_last (axiToBmb_io_bmb_cmd_payload_last ), //o
.io_bmb_cmd_payload_fragment_source (axiToBmb_io_bmb_cmd_payload_fragment_source ), //o
.io_bmb_cmd_payload_fragment_opcode (axiToBmb_io_bmb_cmd_payload_fragment_opcode ), //o
.io_bmb_cmd_payload_fragment_address (axiToBmb_io_bmb_cmd_payload_fragment_address[23:0] ), //o
.io_bmb_cmd_payload_fragment_length (axiToBmb_io_bmb_cmd_payload_fragment_length[9:0] ), //o
.io_bmb_cmd_payload_fragment_data (axiToBmb_io_bmb_cmd_payload_fragment_data[31:0] ), //o
.io_bmb_cmd_payload_fragment_mask (axiToBmb_io_bmb_cmd_payload_fragment_mask[3:0] ), //o
.io_bmb_rsp_valid (bmbHandle_decoder_io_input_rsp_valid ), //i
.io_bmb_rsp_ready (axiToBmb_io_bmb_rsp_ready ), //o
.io_bmb_rsp_payload_last (bmbHandle_decoder_io_input_rsp_payload_last ), //i
.io_bmb_rsp_payload_fragment_source (bmbHandle_decoder_io_input_rsp_payload_fragment_source ), //i
.io_bmb_rsp_payload_fragment_opcode (bmbHandle_decoder_io_input_rsp_payload_fragment_opcode ), //i
.io_bmb_rsp_payload_fragment_data (bmbHandle_decoder_io_input_rsp_payload_fragment_data[31:0]) //i
);
Axi4PeripheralBmbDecoder_86b7e1c47b934a8a97a62bda8ee6a75d bmbHandle_decoder (
.io_input_cmd_valid (axiToBmb_io_bmb_cmd_valid ), //i
.io_input_cmd_ready (bmbHandle_decoder_io_input_cmd_ready ), //o
.io_input_cmd_payload_last (axiToBmb_io_bmb_cmd_payload_last ), //i
.io_input_cmd_payload_fragment_source (axiToBmb_io_bmb_cmd_payload_fragment_source ), //i
.io_input_cmd_payload_fragment_opcode (axiToBmb_io_bmb_cmd_payload_fragment_opcode ), //i
.io_input_cmd_payload_fragment_address (axiToBmb_io_bmb_cmd_payload_fragment_address[23:0] ), //i
.io_input_cmd_payload_fragment_length (axiToBmb_io_bmb_cmd_payload_fragment_length[9:0] ), //i
.io_input_cmd_payload_fragment_data (axiToBmb_io_bmb_cmd_payload_fragment_data[31:0] ), //i
.io_input_cmd_payload_fragment_mask (axiToBmb_io_bmb_cmd_payload_fragment_mask[3:0] ), //i
.io_input_rsp_valid (bmbHandle_decoder_io_input_rsp_valid ), //o
.io_input_rsp_ready (axiToBmb_io_bmb_rsp_ready ), //i
.io_input_rsp_payload_last (bmbHandle_decoder_io_input_rsp_payload_last ), //o
.io_input_rsp_payload_fragment_source (bmbHandle_decoder_io_input_rsp_payload_fragment_source ), //o
.io_input_rsp_payload_fragment_opcode (bmbHandle_decoder_io_input_rsp_payload_fragment_opcode ), //o
.io_input_rsp_payload_fragment_data (bmbHandle_decoder_io_input_rsp_payload_fragment_data[31:0] ), //o
.io_outputs_0_cmd_valid (bmbHandle_decoder_io_outputs_0_cmd_valid ), //o
.io_outputs_0_cmd_ready (bmbHandle_unburstify_io_input_cmd_ready ), //i
.io_outputs_0_cmd_payload_last (bmbHandle_decoder_io_outputs_0_cmd_payload_last ), //o
.io_outputs_0_cmd_payload_fragment_source (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_source ), //o
.io_outputs_0_cmd_payload_fragment_opcode (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //o
.io_outputs_0_cmd_payload_fragment_address (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_address[23:0]), //o
.io_outputs_0_cmd_payload_fragment_length (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_length[9:0] ), //o
.io_outputs_0_cmd_payload_fragment_data (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_data[31:0] ), //o
.io_outputs_0_cmd_payload_fragment_mask (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //o
.io_outputs_0_rsp_valid (bmbHandle_unburstify_io_input_rsp_valid ), //i
.io_outputs_0_rsp_ready (bmbHandle_decoder_io_outputs_0_rsp_ready ), //o
.io_outputs_0_rsp_payload_last (bmbHandle_unburstify_io_input_rsp_payload_last ), //i
.io_outputs_0_rsp_payload_fragment_source (bmbHandle_unburstify_io_input_rsp_payload_fragment_source ), //i
.io_outputs_0_rsp_payload_fragment_opcode (bmbHandle_unburstify_io_input_rsp_payload_fragment_opcode ), //i
.io_outputs_0_rsp_payload_fragment_data (bmbHandle_unburstify_io_input_rsp_payload_fragment_data[31:0] ), //i
.clk (clk ), //i
.reset (reset ) //i
);
Axi4PeripheralBmbUnburstify_86b7e1c47b934a8a97a62bda8ee6a75d bmbHandle_unburstify (
.io_input_cmd_valid (bmbHandle_decoder_io_outputs_0_cmd_valid ), //i
.io_input_cmd_ready (bmbHandle_unburstify_io_input_cmd_ready ), //o
.io_input_cmd_payload_last (bmbHandle_decoder_io_outputs_0_cmd_payload_last ), //i
.io_input_cmd_payload_fragment_source (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_source ), //i
.io_input_cmd_payload_fragment_opcode (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //i
.io_input_cmd_payload_fragment_address (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_address[23:0] ), //i
.io_input_cmd_payload_fragment_length (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_length[9:0] ), //i
.io_input_cmd_payload_fragment_data (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_data[31:0] ), //i
.io_input_cmd_payload_fragment_mask (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //i
.io_input_rsp_valid (bmbHandle_unburstify_io_input_rsp_valid ), //o
.io_input_rsp_ready (bmbHandle_decoder_io_outputs_0_rsp_ready ), //i
.io_input_rsp_payload_last (bmbHandle_unburstify_io_input_rsp_payload_last ), //o
.io_input_rsp_payload_fragment_source (bmbHandle_unburstify_io_input_rsp_payload_fragment_source ), //o
.io_input_rsp_payload_fragment_opcode (bmbHandle_unburstify_io_input_rsp_payload_fragment_opcode ), //o
.io_input_rsp_payload_fragment_data (bmbHandle_unburstify_io_input_rsp_payload_fragment_data[31:0] ), //o
.io_output_cmd_valid (bmbHandle_unburstify_io_output_cmd_valid ), //o
.io_output_cmd_ready (bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready ), //i
.io_output_cmd_payload_last (bmbHandle_unburstify_io_output_cmd_payload_last ), //o
.io_output_cmd_payload_fragment_opcode (bmbHandle_unburstify_io_output_cmd_payload_fragment_opcode ), //o
.io_output_cmd_payload_fragment_address (bmbHandle_unburstify_io_output_cmd_payload_fragment_address[23:0] ), //o
.io_output_cmd_payload_fragment_length (bmbHandle_unburstify_io_output_cmd_payload_fragment_length[1:0] ), //o
.io_output_cmd_payload_fragment_data (bmbHandle_unburstify_io_output_cmd_payload_fragment_data[31:0] ), //o
.io_output_cmd_payload_fragment_mask (bmbHandle_unburstify_io_output_cmd_payload_fragment_mask[3:0] ), //o
.io_output_cmd_payload_fragment_context (bmbHandle_unburstify_io_output_cmd_payload_fragment_context[2:0] ), //o
.io_output_rsp_valid (bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid ), //i
.io_output_rsp_ready (bmbHandle_unburstify_io_output_rsp_ready ), //o
.io_output_rsp_payload_last (bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last ), //i
.io_output_rsp_payload_fragment_opcode (bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode ), //i
.io_output_rsp_payload_fragment_data (bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data[31:0] ), //i
.io_output_rsp_payload_fragment_context (bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context[2:0]), //i
.clk (clk ), //i
.reset (reset ) //i
);
Axi4PeripheralBmbDecoder_1_86b7e1c47b934a8a97a62bda8ee6a75d bmbPeripheral_bmb_decoder (
.io_input_cmd_valid (bmbPeripheral_bmb_cmd_valid ), //i
.io_input_cmd_ready (bmbPeripheral_bmb_decoder_io_input_cmd_ready ), //o
.io_input_cmd_payload_last (bmbPeripheral_bmb_cmd_payload_last ), //i
.io_input_cmd_payload_fragment_opcode (bmbPeripheral_bmb_cmd_payload_fragment_opcode ), //i
.io_input_cmd_payload_fragment_address (bmbPeripheral_bmb_cmd_payload_fragment_address[23:0] ), //i
.io_input_cmd_payload_fragment_length (bmbPeripheral_bmb_cmd_payload_fragment_length[1:0] ), //i
.io_input_cmd_payload_fragment_data (bmbPeripheral_bmb_cmd_payload_fragment_data[31:0] ), //i
.io_input_cmd_payload_fragment_mask (bmbPeripheral_bmb_cmd_payload_fragment_mask[3:0] ), //i
.io_input_cmd_payload_fragment_context (bmbPeripheral_bmb_cmd_payload_fragment_context[2:0] ), //i
.io_input_rsp_valid (bmbPeripheral_bmb_decoder_io_input_rsp_valid ), //o
.io_input_rsp_ready (bmbPeripheral_bmb_rsp_ready ), //i
.io_input_rsp_payload_last (bmbPeripheral_bmb_decoder_io_input_rsp_payload_last ), //o
.io_input_rsp_payload_fragment_opcode (bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_opcode ), //o
.io_input_rsp_payload_fragment_data (bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_data[31:0] ), //o
.io_input_rsp_payload_fragment_context (bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_context[2:0] ), //o
.io_outputs_0_cmd_valid (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_valid ), //o
.io_outputs_0_cmd_ready (bmbPeripheral_bmb_withoutMask_cmd_ready ), //i
.io_outputs_0_cmd_payload_last (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_last ), //o
.io_outputs_0_cmd_payload_fragment_opcode (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //o
.io_outputs_0_cmd_payload_fragment_address (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[23:0]), //o
.io_outputs_0_cmd_payload_fragment_length (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[1:0] ), //o
.io_outputs_0_cmd_payload_fragment_data (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_data[31:0] ), //o
.io_outputs_0_cmd_payload_fragment_mask (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //o
.io_outputs_0_cmd_payload_fragment_context (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_context[2:0] ), //o
.io_outputs_0_rsp_valid (bmbPeripheral_bmb_withoutMask_rsp_valid ), //i
.io_outputs_0_rsp_ready (bmbPeripheral_bmb_decoder_io_outputs_0_rsp_ready ), //o
.io_outputs_0_rsp_payload_last (bmbPeripheral_bmb_withoutMask_rsp_payload_last ), //i
.io_outputs_0_rsp_payload_fragment_opcode (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode ), //i
.io_outputs_0_rsp_payload_fragment_data (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data[31:0] ), //i
.io_outputs_0_rsp_payload_fragment_context (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context[2:0] ), //i
.io_outputs_1_cmd_valid (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_valid ), //o
.io_outputs_1_cmd_ready (bmbPeripheral_bmb_withoutMask_cmd_ready_1 ), //i
.io_outputs_1_cmd_payload_last (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_last ), //o
.io_outputs_1_cmd_payload_fragment_opcode (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode ), //o
.io_outputs_1_cmd_payload_fragment_address (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_address[23:0]), //o
.io_outputs_1_cmd_payload_fragment_length (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_length[1:0] ), //o
.io_outputs_1_cmd_payload_fragment_data (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_data[31:0] ), //o
.io_outputs_1_cmd_payload_fragment_mask (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_mask[3:0] ), //o
.io_outputs_1_cmd_payload_fragment_context (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_context[2:0] ), //o
.io_outputs_1_rsp_valid (bmbPeripheral_bmb_withoutMask_rsp_valid_1 ), //i
.io_outputs_1_rsp_ready (bmbPeripheral_bmb_decoder_io_outputs_1_rsp_ready ), //o
.io_outputs_1_rsp_payload_last (bmbPeripheral_bmb_withoutMask_rsp_payload_last_1 ), //i
.io_outputs_1_rsp_payload_fragment_opcode (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_1 ), //i
.io_outputs_1_rsp_payload_fragment_data (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_1[31:0] ), //i
.io_outputs_1_rsp_payload_fragment_context (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_1[2:0] ), //i
.clk (clk ), //i
.reset (reset ) //i
);
Axi4PeripheralBmbUartCtrl_86b7e1c47b934a8a97a62bda8ee6a75d system_uart_0_io_logic (
.io_bus_cmd_valid (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid ), //i
.io_bus_cmd_ready (system_uart_0_io_logic_io_bus_cmd_ready ), //o
.io_bus_cmd_payload_last (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last ), //i
.io_bus_cmd_payload_fragment_opcode (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode ), //i
.io_bus_cmd_payload_fragment_address (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address[5:0]), //i
.io_bus_cmd_payload_fragment_length (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length[1:0] ), //i
.io_bus_cmd_payload_fragment_data (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data[31:0] ), //i
.io_bus_cmd_payload_fragment_context (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context[2:0]), //i
.io_bus_rsp_valid (system_uart_0_io_logic_io_bus_rsp_valid ), //o
.io_bus_rsp_ready (_zz_io_bus_rsp_ready ), //i
.io_bus_rsp_payload_last (system_uart_0_io_logic_io_bus_rsp_payload_last ), //o
.io_bus_rsp_payload_fragment_opcode (system_uart_0_io_logic_io_bus_rsp_payload_fragment_opcode ), //o
.io_bus_rsp_payload_fragment_data (system_uart_0_io_logic_io_bus_rsp_payload_fragment_data[31:0] ), //o
.io_bus_rsp_payload_fragment_context (system_uart_0_io_logic_io_bus_rsp_payload_fragment_context[2:0] ), //o
.io_uart_txd (system_uart_0_io_logic_io_uart_txd ), //o
.io_uart_rxd (system_uart_0_io_rxd ), //i
.system_uart_0_io_interrupt_source (system_uart_0_io_logic_system_uart_0_io_interrupt_source ), //o
.clk (clk ), //i
.reset (reset ) //i
);
Axi4PeripheralBmbSpiXdrMasterCtrl_86b7e1c47b934a8a97a62bda8ee6a75d system_spi_0_io_logic (
.io_ctrl_cmd_valid (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid ), //i
.io_ctrl_cmd_ready (system_spi_0_io_logic_io_ctrl_cmd_ready ), //o
.io_ctrl_cmd_payload_last (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last ), //i
.io_ctrl_cmd_payload_fragment_opcode (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode ), //i
.io_ctrl_cmd_payload_fragment_address (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address[11:0]), //i
.io_ctrl_cmd_payload_fragment_length (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length[1:0] ), //i
.io_ctrl_cmd_payload_fragment_data (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data[31:0] ), //i
.io_ctrl_cmd_payload_fragment_context (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context[2:0] ), //i
.io_ctrl_rsp_valid (system_spi_0_io_logic_io_ctrl_rsp_valid ), //o
.io_ctrl_rsp_ready (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i
.io_ctrl_rsp_payload_last (system_spi_0_io_logic_io_ctrl_rsp_payload_last ), //o
.io_ctrl_rsp_payload_fragment_opcode (system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_opcode ), //o
.io_ctrl_rsp_payload_fragment_data (system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_data[31:0] ), //o
.io_ctrl_rsp_payload_fragment_context (system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_context[2:0] ), //o
.io_spi_sclk_write (system_spi_0_io_logic_io_spi_sclk_write ), //o
.io_spi_data_0_writeEnable (system_spi_0_io_logic_io_spi_data_0_writeEnable ), //o
.io_spi_data_0_read (system_spi_0_io_data_0_read ), //i
.io_spi_data_0_write (system_spi_0_io_logic_io_spi_data_0_write ), //o
.io_spi_data_1_writeEnable (system_spi_0_io_logic_io_spi_data_1_writeEnable ), //o
.io_spi_data_1_read (system_spi_0_io_data_1_read ), //i
.io_spi_data_1_write (system_spi_0_io_logic_io_spi_data_1_write ), //o
.io_spi_data_2_writeEnable (system_spi_0_io_logic_io_spi_data_2_writeEnable ), //o
.io_spi_data_2_read (system_spi_0_io_data_2_read ), //i
.io_spi_data_2_write (system_spi_0_io_logic_io_spi_data_2_write ), //o
.io_spi_data_3_writeEnable (system_spi_0_io_logic_io_spi_data_3_writeEnable ), //o
.io_spi_data_3_read (system_spi_0_io_data_3_read ), //i
.io_spi_data_3_write (system_spi_0_io_logic_io_spi_data_3_write ), //o
.io_spi_ss (system_spi_0_io_logic_io_spi_ss[3:0] ), //o
.system_spi_0_io_interrupt_source (system_spi_0_io_logic_system_spi_0_io_interrupt_source ), //o
.clk (clk ), //i
.reset (reset ) //i
);
assign axi_aw_halfPipe_fire = (axi_aw_halfPipe_valid && axi_aw_halfPipe_ready);
assign axi_awready = (! axi_aw_rValid);
assign axi_aw_halfPipe_valid = axi_aw_rValid;
assign axi_aw_halfPipe_payload_addr = axi_aw_rData_addr;
assign axi_aw_halfPipe_payload_len = axi_aw_rData_len;
assign axi_aw_halfPipe_payload_size = axi_aw_rData_size;
assign axi_aw_halfPipe_payload_cache = axi_aw_rData_cache;
assign axi_aw_halfPipe_payload_prot = axi_aw_rData_prot;
assign axi_aw_halfPipe_ready = streamArbiter_io_inputs_1_ready;
assign axi_w_halfPipe_fire = (axi_w_halfPipe_valid && axi_w_halfPipe_ready);
assign axi_wready = (! axi_w_rValid);
assign axi_w_halfPipe_valid = axi_w_rValid;
assign axi_w_halfPipe_payload_data = axi_w_rData_data;
assign axi_w_halfPipe_payload_strb = axi_w_rData_strb;
assign axi_w_halfPipe_payload_last = axi_w_rData_last;
assign axi_w_halfPipe_ready = axiShared_w_ready;
assign _zz_axiShared_b_ready = (! _zz_axi_bvalid_1);
assign _zz_axi_bvalid = _zz_axi_bvalid_1;
assign axi_bvalid = _zz_axi_bvalid;
assign axi_bresp = _zz_axi_bresp;
assign axi_ar_halfPipe_fire = (axi_ar_halfPipe_valid && axi_ar_halfPipe_ready);
assign axi_arready = (! axi_ar_rValid);
assign axi_ar_halfPipe_valid = axi_ar_rValid;
assign axi_ar_halfPipe_payload_addr = axi_ar_rData_addr;
assign axi_ar_halfPipe_payload_len = axi_ar_rData_len;
assign axi_ar_halfPipe_payload_size = axi_ar_rData_size;
assign axi_ar_halfPipe_payload_cache = axi_ar_rData_cache;
assign axi_ar_halfPipe_payload_prot = axi_ar_rData_prot;
assign axi_ar_halfPipe_ready = streamArbiter_io_inputs_0_ready;
assign _zz_axiShared_r_ready = (! _zz_axi_rvalid_1);
assign _zz_axi_rvalid = _zz_axi_rvalid_1;
assign axi_rvalid = _zz_axi_rvalid;
assign axi_rdata = _zz_axi_rdata;
assign axi_rresp = _zz_axi_rresp;
assign axi_rlast = _zz_axi_rlast;
assign axiShared_arw_valid = streamArbiter_io_output_valid;
assign axiShared_arw_payload_addr = streamArbiter_io_output_payload_addr;
assign axiShared_arw_payload_len = streamArbiter_io_output_payload_len;
assign axiShared_arw_payload_size = streamArbiter_io_output_payload_size;
assign axiShared_arw_payload_cache = streamArbiter_io_output_payload_cache;
assign axiShared_arw_payload_prot = streamArbiter_io_output_payload_prot;
assign axiShared_arw_payload_write = streamArbiter_io_chosenOH[1];
assign axiShared_w_valid = axi_w_halfPipe_valid;
assign axiShared_w_payload_data = axi_w_halfPipe_payload_data;
assign axiShared_w_payload_strb = axi_w_halfPipe_payload_strb;
assign axiShared_w_payload_last = axi_w_halfPipe_payload_last;
assign axiShared_b_ready = _zz_axiShared_b_ready;
assign axiShared_r_ready = _zz_axiShared_r_ready;
assign axiShared_arw_ready = axiToBmb_io_axi_arw_ready;
assign axiShared_w_ready = axiToBmb_io_axi_w_ready;
assign axiShared_b_valid = axiToBmb_io_axi_b_valid;
assign axiShared_b_payload_resp = axiToBmb_io_axi_b_payload_resp;
assign axiShared_r_valid = axiToBmb_io_axi_r_valid;
assign axiShared_r_payload_data = axiToBmb_io_axi_r_payload_data;
assign axiShared_r_payload_last = axiToBmb_io_axi_r_payload_last;
assign axiShared_r_payload_resp = axiToBmb_io_axi_r_payload_resp;
assign bmbPeripheral_bmb_cmd_valid = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid;
assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = bmbPeripheral_bmb_cmd_ready;
assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = bmbPeripheral_bmb_rsp_valid;
assign bmbPeripheral_bmb_rsp_ready = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready;
assign bmbPeripheral_bmb_cmd_payload_last = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last;
assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = bmbPeripheral_bmb_rsp_payload_last;
assign bmbPeripheral_bmb_cmd_payload_fragment_opcode = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode;
assign bmbPeripheral_bmb_cmd_payload_fragment_address = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address;
assign bmbPeripheral_bmb_cmd_payload_fragment_length = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length;
assign bmbPeripheral_bmb_cmd_payload_fragment_data = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data;
assign bmbPeripheral_bmb_cmd_payload_fragment_mask = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask;
assign bmbPeripheral_bmb_cmd_payload_fragment_context = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context;
assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = bmbPeripheral_bmb_rsp_payload_fragment_opcode;
assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = bmbPeripheral_bmb_rsp_payload_fragment_data;
assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = bmbPeripheral_bmb_rsp_payload_fragment_context;
assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbHandle_unburstify_io_output_cmd_valid;
assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbHandle_unburstify_io_output_rsp_ready;
assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbHandle_unburstify_io_output_cmd_payload_last;
assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbHandle_unburstify_io_output_cmd_payload_fragment_opcode;
assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbHandle_unburstify_io_output_cmd_payload_fragment_address;
assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbHandle_unburstify_io_output_cmd_payload_fragment_length;
assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbHandle_unburstify_io_output_cmd_payload_fragment_data;
assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = bmbHandle_unburstify_io_output_cmd_payload_fragment_mask;
assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = bmbHandle_unburstify_io_output_cmd_payload_fragment_context;
assign bmbPeripheral_bmb_cmd_ready = bmbPeripheral_bmb_decoder_io_input_cmd_ready;
assign bmbPeripheral_bmb_rsp_valid = bmbPeripheral_bmb_decoder_io_input_rsp_valid;
assign bmbPeripheral_bmb_rsp_payload_last = bmbPeripheral_bmb_decoder_io_input_rsp_payload_last;
assign bmbPeripheral_bmb_rsp_payload_fragment_opcode = bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_opcode;
assign bmbPeripheral_bmb_rsp_payload_fragment_data = bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_data;
assign bmbPeripheral_bmb_rsp_payload_fragment_context = bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_context;
assign system_uart_0_io_txd = system_uart_0_io_logic_io_uart_txd;
assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire = (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid && system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready);
assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = (! system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid);
assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid;
assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last;
assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode;
assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address;
assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length;
assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data;
assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context;
assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready = system_uart_0_io_logic_io_bus_cmd_ready;
assign _zz_io_bus_rsp_ready = (! _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1);
assign _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1;
assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid;
assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last;
assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode;
assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data;
assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context;
assign system_uart_0_io_interrupt = system_uart_0_io_logic_system_uart_0_io_interrupt_source;
assign system_spi_0_io_interrupt = system_spi_0_io_logic_system_spi_0_io_interrupt_source;
assign system_spi_0_io_sclk_write = system_spi_0_io_logic_io_spi_sclk_write;
assign system_spi_0_io_data_0_writeEnable = system_spi_0_io_logic_io_spi_data_0_writeEnable;
assign system_spi_0_io_data_0_write = system_spi_0_io_logic_io_spi_data_0_write;
assign system_spi_0_io_data_1_writeEnable = system_spi_0_io_logic_io_spi_data_1_writeEnable;
assign system_spi_0_io_data_1_write = system_spi_0_io_logic_io_spi_data_1_write;
assign system_spi_0_io_data_2_writeEnable = system_spi_0_io_logic_io_spi_data_2_writeEnable;
assign system_spi_0_io_data_2_write = system_spi_0_io_logic_io_spi_data_2_write;
assign system_spi_0_io_data_3_writeEnable = system_spi_0_io_logic_io_spi_data_3_writeEnable;
assign system_spi_0_io_data_3_write = system_spi_0_io_logic_io_spi_data_3_write;
assign system_spi_0_io_ss = system_spi_0_io_logic_io_spi_ss;
assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire = (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid && system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready);
assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = (! system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid);
assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid;
assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last;
assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode;
assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address;
assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length;
assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data;
assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context;
assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready = system_spi_0_io_logic_io_ctrl_cmd_ready;
assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_spi_0_io_logic_io_ctrl_rsp_valid;
assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_spi_0_io_logic_io_ctrl_rsp_payload_last;
assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_opcode;
assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_data;
assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_context;
assign bmbPeripheral_bmb_withoutMask_cmd_valid = bmbPeripheral_bmb_decoder_io_outputs_0_cmd_valid;
assign bmbPeripheral_bmb_withoutMask_rsp_ready = bmbPeripheral_bmb_decoder_io_outputs_0_rsp_ready;
assign bmbPeripheral_bmb_withoutMask_cmd_payload_last = bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_last;
assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode = bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode;
assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address = bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_address;
assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length = bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_length;
assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data = bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_data;
assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context = bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_context;
assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbPeripheral_bmb_withoutMask_cmd_valid;
assign bmbPeripheral_bmb_withoutMask_cmd_ready = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready;
assign bmbPeripheral_bmb_withoutMask_rsp_valid = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid;
assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbPeripheral_bmb_withoutMask_rsp_ready;
assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbPeripheral_bmb_withoutMask_cmd_payload_last;
assign bmbPeripheral_bmb_withoutMask_rsp_payload_last = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last;
assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode;
assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address[5:0];
assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length;
assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data;
assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context;
assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode;
assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data;
assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context;
assign bmbPeripheral_bmb_withoutMask_cmd_valid_1 = bmbPeripheral_bmb_decoder_io_outputs_1_cmd_valid;
assign bmbPeripheral_bmb_withoutMask_rsp_ready_1 = bmbPeripheral_bmb_decoder_io_outputs_1_rsp_ready;
assign bmbPeripheral_bmb_withoutMask_cmd_payload_last_1 = bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_last;
assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_1 = bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode;
assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_1 = bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_address;
assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_1 = bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_length;
assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_1 = bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_data;
assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_1 = bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_context;
assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbPeripheral_bmb_withoutMask_cmd_valid_1;
assign bmbPeripheral_bmb_withoutMask_cmd_ready_1 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready;
assign bmbPeripheral_bmb_withoutMask_rsp_valid_1 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid;
assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbPeripheral_bmb_withoutMask_rsp_ready_1;
assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbPeripheral_bmb_withoutMask_cmd_payload_last_1;
assign bmbPeripheral_bmb_withoutMask_rsp_payload_last_1 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last;
assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_1;
assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_1[11:0];
assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_1;
assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_1;
assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_1;
assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_1 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode;
assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_1 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data;
assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_1 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context;
always @(posedge clk) begin
if(reset) begin
axi_aw_rValid <= 1'b0;
axi_w_rValid <= 1'b0;
_zz_axi_bvalid_1 <= 1'b0;
axi_ar_rValid <= 1'b0;
_zz_axi_rvalid_1 <= 1'b0;
system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0;
_zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b0;
system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0;
end else begin
if(axi_awvalid) begin
axi_aw_rValid <= 1'b1;
end
if(axi_aw_halfPipe_fire) begin
axi_aw_rValid <= 1'b0;
end
if(axi_wvalid) begin
axi_w_rValid <= 1'b1;
end
if(axi_w_halfPipe_fire) begin
axi_w_rValid <= 1'b0;
end
if(axiShared_b_valid) begin
_zz_axi_bvalid_1 <= 1'b1;
end
if((_zz_axi_bvalid && axi_bready)) begin
_zz_axi_bvalid_1 <= 1'b0;
end
if(axi_arvalid) begin
axi_ar_rValid <= 1'b1;
end
if(axi_ar_halfPipe_fire) begin
axi_ar_rValid <= 1'b0;
end
if(axiShared_r_valid) begin
_zz_axi_rvalid_1 <= 1'b1;
end
if((_zz_axi_rvalid && axi_rready)) begin
_zz_axi_rvalid_1 <= 1'b0;
end
if(system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid) begin
system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b1;
end
if(system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire) begin
system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0;
end
if(system_uart_0_io_logic_io_bus_rsp_valid) begin
_zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b1;
end
if((_zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid && system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready)) begin
_zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b0;
end
if(system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid) begin
system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b1;
end
if(system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire) begin
system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0;
end
end
end
always @(posedge clk) begin
if(axi_awready) begin
axi_aw_rData_addr <= axi_awaddr;
axi_aw_rData_len <= axi_awlen;
axi_aw_rData_size <= axi_awsize;
axi_aw_rData_cache <= axi_awcache;
axi_aw_rData_prot <= axi_awprot;
end
if(axi_wready) begin
axi_w_rData_data <= axi_wdata;
axi_w_rData_strb <= axi_wstrb;
axi_w_rData_last <= axi_wlast;
end
if(_zz_axiShared_b_ready) begin
_zz_axi_bresp <= axiShared_b_payload_resp;
end
if(axi_arready) begin
axi_ar_rData_addr <= axi_araddr;
axi_ar_rData_len <= axi_arlen;
axi_ar_rData_size <= axi_arsize;
axi_ar_rData_cache <= axi_arcache;
axi_ar_rData_prot <= axi_arprot;
end
if(_zz_axiShared_r_ready) begin
_zz_axi_rdata <= axiShared_r_payload_data;
_zz_axi_rresp <= axiShared_r_payload_resp;
_zz_axi_rlast <= axiShared_r_payload_last;
end
if(system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready) begin
system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last;
system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode;
system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address;
system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length;
system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data;
system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context;
end
if(_zz_io_bus_rsp_ready) begin
_zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last <= system_uart_0_io_logic_io_bus_rsp_payload_last;
_zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode <= system_uart_0_io_logic_io_bus_rsp_payload_fragment_opcode;
_zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data <= system_uart_0_io_logic_io_bus_rsp_payload_fragment_data;
_zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context <= system_uart_0_io_logic_io_bus_rsp_payload_fragment_context;
end
if(system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready) begin
system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last;
system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode;
system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address;
system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length;
system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data;
system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context;
end
end
endmodule
module Axi4PeripheralBmbSpiXdrMasterCtrl_86b7e1c47b934a8a97a62bda8ee6a75d (
input wire io_ctrl_cmd_valid,
output wire io_ctrl_cmd_ready,
input wire io_ctrl_cmd_payload_last,
input wire [0:0] io_ctrl_cmd_payload_fragment_opcode,
input wire [11:0] io_ctrl_cmd_payload_fragment_address,
input wire [1:0] io_ctrl_cmd_payload_fragment_length,
input wire [31:0] io_ctrl_cmd_payload_fragment_data,
input wire [2:0] io_ctrl_cmd_payload_fragment_context,
output wire io_ctrl_rsp_valid,
input wire io_ctrl_rsp_ready,
output wire io_ctrl_rsp_payload_last,
output wire [0:0] io_ctrl_rsp_payload_fragment_opcode,
output wire [31:0] io_ctrl_rsp_payload_fragment_data,
output wire [2:0] io_ctrl_rsp_payload_fragment_context,
output wire [0:0] io_spi_sclk_write,
output wire io_spi_data_0_writeEnable,
input wire [0:0] io_spi_data_0_read,
output wire [0:0] io_spi_data_0_write,
output wire io_spi_data_1_writeEnable,
input wire [0:0] io_spi_data_1_read,
output wire [0:0] io_spi_data_1_write,
output wire io_spi_data_2_writeEnable,
input wire [0:0] io_spi_data_2_read,
output wire [0:0] io_spi_data_2_write,
output wire io_spi_data_3_writeEnable,
input wire [0:0] io_spi_data_3_read,
output wire [0:0] io_spi_data_3_write,
output wire [3:0] io_spi_ss,
output wire system_spi_0_io_interrupt_source,
input wire clk,
input wire reset
);
wire ctrl_io_rsp_queueWithOccupancy_io_pop_ready;
wire ctrl_io_cmd_ready;
wire ctrl_io_rsp_valid;
wire [7:0] ctrl_io_rsp_payload_data;
wire [0:0] ctrl_io_spi_sclk_write;
wire [3:0] ctrl_io_spi_ss;
wire [0:0] ctrl_io_spi_data_0_write;
wire ctrl_io_spi_data_0_writeEnable;
wire [0:0] ctrl_io_spi_data_1_write;
wire ctrl_io_spi_data_1_writeEnable;
wire [0:0] ctrl_io_spi_data_2_write;
wire ctrl_io_spi_data_2_writeEnable;
wire [0:0] ctrl_io_spi_data_3_write;
wire ctrl_io_spi_data_3_writeEnable;
wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready;
wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid;
wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind;
wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read;
wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write;
wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data;
wire [8:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_occupancy;
wire [8:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability;
wire ctrl_io_rsp_queueWithOccupancy_io_push_ready;
wire ctrl_io_rsp_queueWithOccupancy_io_pop_valid;
wire [7:0] ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data;
wire [8:0] ctrl_io_rsp_queueWithOccupancy_io_occupancy;
wire [8:0] ctrl_io_rsp_queueWithOccupancy_io_availability;
wire factory_readErrorFlag;
wire factory_writeErrorFlag;
wire factory_readHaltTrigger;
wire factory_writeHaltTrigger;
wire factory_rsp_valid;
wire factory_rsp_ready;
wire factory_rsp_payload_last;
reg [0:0] factory_rsp_payload_fragment_opcode;
reg [31:0] factory_rsp_payload_fragment_data;
wire [2:0] factory_rsp_payload_fragment_context;
wire _zz_factory_rsp_ready;
reg _zz_factory_rsp_ready_1;
wire _zz_io_ctrl_rsp_valid;
reg _zz_io_ctrl_rsp_valid_1;
reg _zz_io_ctrl_rsp_payload_last;
reg [0:0] _zz_io_ctrl_rsp_payload_fragment_opcode;
reg [31:0] _zz_io_ctrl_rsp_payload_fragment_data;
reg [2:0] _zz_io_ctrl_rsp_payload_fragment_context;
wire when_Stream_l375;
wire factory_askWrite;
wire factory_askRead;
wire io_ctrl_cmd_fire;
wire factory_doWrite;
wire factory_doRead;
wire when_BmbSlaveFactory_l33;
wire when_BmbSlaveFactory_l35;
wire [31:0] mapping_cmdLogic_writeData;
reg mapping_cmdLogic_doRegular;
reg mapping_cmdLogic_doWriteLarge;
reg mapping_cmdLogic_doReadWriteLarge;
wire mapping_cmdLogic_streamUnbuffered_valid;
wire mapping_cmdLogic_streamUnbuffered_ready;
wire mapping_cmdLogic_streamUnbuffered_payload_kind;
wire mapping_cmdLogic_streamUnbuffered_payload_read;
wire mapping_cmdLogic_streamUnbuffered_payload_write;
wire [7:0] mapping_cmdLogic_streamUnbuffered_payload_data;
wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid;
reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready;
wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind;
wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read;
wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write;
wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data;
reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN;
reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind;
reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read;
reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write;
reg [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data;
wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid;
wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready;
wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind;
wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read;
wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write;
wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data;
reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid;
reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind;
reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read;
reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write;
reg [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data;
wire when_Stream_l375_1;
wire ctrl_io_rsp_toStream_valid;
wire ctrl_io_rsp_toStream_ready;
wire [7:0] ctrl_io_rsp_toStream_payload_data;
reg _zz_io_pop_ready;
reg _zz_io_pop_ready_1;
reg mapping_interruptCtrl_cmdIntEnable;
reg mapping_interruptCtrl_rspIntEnable;
wire mapping_interruptCtrl_cmdInt;
wire mapping_interruptCtrl_rspInt;
wire mapping_interruptCtrl_interrupt;
reg _zz_io_config_kind_cpol;
reg _zz_io_config_kind_cpha;
reg [1:0] _zz_io_config_mod;
reg [11:0] _zz_io_config_sclkToggle;
reg [11:0] _zz_io_config_ss_setup;
reg [11:0] _zz_io_config_ss_hold;
reg [11:0] _zz_io_config_ss_disable;
reg [3:0] _zz_io_config_ss_activeHigh;
wire [1:0] _zz_io_config_kind_cpol_1;
Axi4PeripheralTopLevel_86b7e1c47b934a8a97a62bda8ee6a75d ctrl (
.io_config_kind_cpol (_zz_io_config_kind_cpol ), //i
.io_config_kind_cpha (_zz_io_config_kind_cpha ), //i
.io_config_sclkToggle (_zz_io_config_sclkToggle[11:0] ), //i
.io_config_mod (_zz_io_config_mod[1:0] ), //i
.io_config_ss_activeHigh (_zz_io_config_ss_activeHigh[3:0] ), //i
.io_config_ss_setup (_zz_io_config_ss_setup[11:0] ), //i
.io_config_ss_hold (_zz_io_config_ss_hold[11:0] ), //i
.io_config_ss_disable (_zz_io_config_ss_disable[11:0] ), //i
.io_cmd_valid (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid ), //i
.io_cmd_ready (ctrl_io_cmd_ready ), //o
.io_cmd_payload_kind (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind ), //i
.io_cmd_payload_read (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read ), //i
.io_cmd_payload_write (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write ), //i
.io_cmd_payload_data (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data[7:0]), //i
.io_rsp_valid (ctrl_io_rsp_valid ), //o
.io_rsp_payload_data (ctrl_io_rsp_payload_data[7:0] ), //o
.io_spi_sclk_write (ctrl_io_spi_sclk_write ), //o
.io_spi_data_0_writeEnable (ctrl_io_spi_data_0_writeEnable ), //o
.io_spi_data_0_read (io_spi_data_0_read ), //i
.io_spi_data_0_write (ctrl_io_spi_data_0_write ), //o
.io_spi_data_1_writeEnable (ctrl_io_spi_data_1_writeEnable ), //o
.io_spi_data_1_read (io_spi_data_1_read ), //i
.io_spi_data_1_write (ctrl_io_spi_data_1_write ), //o
.io_spi_data_2_writeEnable (ctrl_io_spi_data_2_writeEnable ), //o
.io_spi_data_2_read (io_spi_data_2_read ), //i
.io_spi_data_2_write (ctrl_io_spi_data_2_write ), //o
.io_spi_data_3_writeEnable (ctrl_io_spi_data_3_writeEnable ), //o
.io_spi_data_3_read (io_spi_data_3_read ), //i
.io_spi_data_3_write (ctrl_io_spi_data_3_write ), //o
.io_spi_ss (ctrl_io_spi_ss[3:0] ), //o
.clk (clk ), //i
.reset (reset ) //i
);
Axi4PeripheralStreamFifo_2_86b7e1c47b934a8a97a62bda8ee6a75d mapping_cmdLogic_streamUnbuffered_queueWithAvailability (
.io_push_valid (mapping_cmdLogic_streamUnbuffered_valid ), //i
.io_push_ready (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready ), //o
.io_push_payload_kind (mapping_cmdLogic_streamUnbuffered_payload_kind ), //i
.io_push_payload_read (mapping_cmdLogic_streamUnbuffered_payload_read ), //i
.io_push_payload_write (mapping_cmdLogic_streamUnbuffered_payload_write ), //i
.io_push_payload_data (mapping_cmdLogic_streamUnbuffered_payload_data[7:0] ), //i
.io_pop_valid (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid ), //o
.io_pop_ready (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN ), //i
.io_pop_payload_kind (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind ), //o
.io_pop_payload_read (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read ), //o
.io_pop_payload_write (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write ), //o
.io_pop_payload_data (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data[7:0]), //o
.io_flush (1'b0 ), //i
.io_occupancy (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_occupancy[8:0] ), //o
.io_availability (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability[8:0] ), //o
.clk (clk ), //i
.reset (reset ) //i
);
Axi4PeripheralStreamFifo_3_86b7e1c47b934a8a97a62bda8ee6a75d ctrl_io_rsp_queueWithOccupancy (
.io_push_valid (ctrl_io_rsp_toStream_valid ), //i
.io_push_ready (ctrl_io_rsp_queueWithOccupancy_io_push_ready ), //o
.io_push_payload_data (ctrl_io_rsp_toStream_payload_data[7:0] ), //i
.io_pop_valid (ctrl_io_rsp_queueWithOccupancy_io_pop_valid ), //o
.io_pop_ready (ctrl_io_rsp_queueWithOccupancy_io_pop_ready ), //i
.io_pop_payload_data (ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data[7:0]), //o
.io_flush (1'b0 ), //i
.io_occupancy (ctrl_io_rsp_queueWithOccupancy_io_occupancy[8:0] ), //o
.io_availability (ctrl_io_rsp_queueWithOccupancy_io_availability[8:0] ), //o
.clk (clk ), //i
.reset (reset ) //i
);
assign factory_readErrorFlag = 1'b0;
assign factory_writeErrorFlag = 1'b0;
assign factory_readHaltTrigger = 1'b0;
assign factory_writeHaltTrigger = 1'b0;
assign _zz_factory_rsp_ready = (! (factory_readHaltTrigger || factory_writeHaltTrigger));
assign factory_rsp_ready = (_zz_factory_rsp_ready_1 && _zz_factory_rsp_ready);
always @(*) begin
_zz_factory_rsp_ready_1 = io_ctrl_rsp_ready;
if(when_Stream_l375) begin
_zz_factory_rsp_ready_1 = 1'b1;
end
end
assign when_Stream_l375 = (! _zz_io_ctrl_rsp_valid);
assign _zz_io_ctrl_rsp_valid = _zz_io_ctrl_rsp_valid_1;
assign io_ctrl_rsp_valid = _zz_io_ctrl_rsp_valid;
assign io_ctrl_rsp_payload_last = _zz_io_ctrl_rsp_payload_last;
assign io_ctrl_rsp_payload_fragment_opcode = _zz_io_ctrl_rsp_payload_fragment_opcode;
assign io_ctrl_rsp_payload_fragment_data = _zz_io_ctrl_rsp_payload_fragment_data;
assign io_ctrl_rsp_payload_fragment_context = _zz_io_ctrl_rsp_payload_fragment_context;
assign factory_askWrite = (io_ctrl_cmd_valid && (io_ctrl_cmd_payload_fragment_opcode == 1'b1));
assign factory_askRead = (io_ctrl_cmd_valid && (io_ctrl_cmd_payload_fragment_opcode == 1'b0));
assign io_ctrl_cmd_fire = (io_ctrl_cmd_valid && io_ctrl_cmd_ready);
assign factory_doWrite = (io_ctrl_cmd_fire && (io_ctrl_cmd_payload_fragment_opcode == 1'b1));
assign factory_doRead = (io_ctrl_cmd_fire && (io_ctrl_cmd_payload_fragment_opcode == 1'b0));
assign factory_rsp_valid = io_ctrl_cmd_valid;
assign io_ctrl_cmd_ready = factory_rsp_ready;
assign factory_rsp_payload_last = 1'b1;
assign when_BmbSlaveFactory_l33 = (factory_doWrite && factory_writeErrorFlag);
always @(*) begin
if(when_BmbSlaveFactory_l33) begin
factory_rsp_payload_fragment_opcode = 1'b1;
end else begin
if(when_BmbSlaveFactory_l35) begin
factory_rsp_payload_fragment_opcode = 1'b1;
end else begin
factory_rsp_payload_fragment_opcode = 1'b0;
end
end
end
assign when_BmbSlaveFactory_l35 = (factory_doRead && factory_readErrorFlag);
always @(*) begin
factory_rsp_payload_fragment_data = 32'h0;
case(io_ctrl_cmd_payload_fragment_address)
12'h0 : begin
factory_rsp_payload_fragment_data[31 : 31] = (! ctrl_io_rsp_queueWithOccupancy_io_pop_valid);
factory_rsp_payload_fragment_data[7 : 0] = ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data;
end
12'h004 : begin
factory_rsp_payload_fragment_data[8 : 0] = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability;
factory_rsp_payload_fragment_data[24 : 16] = ctrl_io_rsp_queueWithOccupancy_io_occupancy;
end
12'h00c : begin
factory_rsp_payload_fragment_data[16 : 16] = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid;
factory_rsp_payload_fragment_data[0 : 0] = mapping_interruptCtrl_cmdIntEnable;
factory_rsp_payload_fragment_data[1 : 1] = mapping_interruptCtrl_rspIntEnable;
factory_rsp_payload_fragment_data[8 : 8] = mapping_interruptCtrl_cmdInt;
factory_rsp_payload_fragment_data[9 : 9] = mapping_interruptCtrl_rspInt;
end
12'h058 : begin
factory_rsp_payload_fragment_data[7 : 0] = ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data;
end
default : begin
end
endcase
end
assign factory_rsp_payload_fragment_context = io_ctrl_cmd_payload_fragment_context;
always @(*) begin
mapping_cmdLogic_doRegular = 1'b0;
case(io_ctrl_cmd_payload_fragment_address)
12'h0 : begin
if(factory_doWrite) begin
mapping_cmdLogic_doRegular = 1'b1;
end
end
default : begin
end
endcase
end
always @(*) begin
mapping_cmdLogic_doWriteLarge = 1'b0;
case(io_ctrl_cmd_payload_fragment_address)
12'h050 : begin
if(factory_doWrite) begin
mapping_cmdLogic_doWriteLarge = 1'b1;
end
end
default : begin
end
endcase
end
always @(*) begin
mapping_cmdLogic_doReadWriteLarge = 1'b0;
case(io_ctrl_cmd_payload_fragment_address)
12'h054 : begin
if(factory_doWrite) begin
mapping_cmdLogic_doReadWriteLarge = 1'b1;
end
end
default : begin
end
endcase
end
assign mapping_cmdLogic_streamUnbuffered_valid = ((mapping_cmdLogic_doRegular || mapping_cmdLogic_doWriteLarge) || mapping_cmdLogic_doReadWriteLarge);
assign mapping_cmdLogic_streamUnbuffered_payload_write = (((mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[8]) || mapping_cmdLogic_doWriteLarge) || mapping_cmdLogic_doReadWriteLarge);
assign mapping_cmdLogic_streamUnbuffered_payload_read = ((mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[9]) || mapping_cmdLogic_doReadWriteLarge);
assign mapping_cmdLogic_streamUnbuffered_payload_kind = (mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[11]);
assign mapping_cmdLogic_streamUnbuffered_payload_data = mapping_cmdLogic_writeData[7:0];
assign mapping_cmdLogic_streamUnbuffered_ready = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready;
assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid || (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN));
assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind);
assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read);
assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write);
assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data);
always @(*) begin
mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready;
if(when_Stream_l375_1) begin
mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready = 1'b1;
end
end
assign when_Stream_l375_1 = (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid);
assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid;
assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind;
assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read;
assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write;
assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data;
assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready = ctrl_io_cmd_ready;
assign ctrl_io_rsp_toStream_valid = ctrl_io_rsp_valid;
assign ctrl_io_rsp_toStream_payload_data = ctrl_io_rsp_payload_data;
assign ctrl_io_rsp_toStream_ready = ctrl_io_rsp_queueWithOccupancy_io_push_ready;
always @(*) begin
_zz_io_pop_ready = 1'b0;
case(io_ctrl_cmd_payload_fragment_address)
12'h0 : begin
if(factory_doRead) begin
_zz_io_pop_ready = 1'b1;
end
end
default : begin
end
endcase
end
always @(*) begin
_zz_io_pop_ready_1 = 1'b0;
case(io_ctrl_cmd_payload_fragment_address)
12'h058 : begin
if(factory_doRead) begin
_zz_io_pop_ready_1 = 1'b1;
end
end
default : begin
end
endcase
end
assign ctrl_io_rsp_queueWithOccupancy_io_pop_ready = (_zz_io_pop_ready || _zz_io_pop_ready_1);
assign mapping_interruptCtrl_cmdInt = (mapping_interruptCtrl_cmdIntEnable && (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid));
assign mapping_interruptCtrl_rspInt = (mapping_interruptCtrl_rspIntEnable && ctrl_io_rsp_queueWithOccupancy_io_pop_valid);
assign mapping_interruptCtrl_interrupt = (mapping_interruptCtrl_rspInt || mapping_interruptCtrl_cmdInt);
assign io_spi_sclk_write = ctrl_io_spi_sclk_write;
assign io_spi_data_0_writeEnable = ctrl_io_spi_data_0_writeEnable;
assign io_spi_data_0_write = ctrl_io_spi_data_0_write;
assign io_spi_data_1_writeEnable = ctrl_io_spi_data_1_writeEnable;
assign io_spi_data_1_write = ctrl_io_spi_data_1_write;
assign io_spi_data_2_writeEnable = ctrl_io_spi_data_2_writeEnable;
assign io_spi_data_2_write = ctrl_io_spi_data_2_write;
assign io_spi_data_3_writeEnable = ctrl_io_spi_data_3_writeEnable;
assign io_spi_data_3_write = ctrl_io_spi_data_3_write;
assign io_spi_ss = ctrl_io_spi_ss;
assign system_spi_0_io_interrupt_source = mapping_interruptCtrl_interrupt;
assign mapping_cmdLogic_writeData = io_ctrl_cmd_payload_fragment_data[31 : 0];
assign _zz_io_config_kind_cpol_1 = io_ctrl_cmd_payload_fragment_data[1 : 0];
always @(posedge clk) begin
if(reset) begin
_zz_io_ctrl_rsp_valid_1 <= 1'b0;
mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN <= 1'b1;
mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid <= 1'b0;
mapping_interruptCtrl_cmdIntEnable <= 1'b0;
mapping_interruptCtrl_rspIntEnable <= 1'b0;
_zz_io_config_ss_activeHigh <= 4'b0000;
end else begin
if(_zz_factory_rsp_ready_1) begin
_zz_io_ctrl_rsp_valid_1 <= (factory_rsp_valid && _zz_factory_rsp_ready);
end
if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid) begin
mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN <= 1'b0;
end
if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin
mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN <= 1'b1;
end
if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin
mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid;
end
case(io_ctrl_cmd_payload_fragment_address)
12'h00c : begin
if(factory_doWrite) begin
mapping_interruptCtrl_cmdIntEnable <= io_ctrl_cmd_payload_fragment_data[0];
mapping_interruptCtrl_rspIntEnable <= io_ctrl_cmd_payload_fragment_data[1];
end
end
12'h030 : begin
if(factory_doWrite) begin
_zz_io_config_ss_activeHigh <= io_ctrl_cmd_payload_fragment_data[3 : 0];
end
end
default : begin
end
endcase
end
end
always @(posedge clk) begin
if(_zz_factory_rsp_ready_1) begin
_zz_io_ctrl_rsp_payload_last <= factory_rsp_payload_last;
_zz_io_ctrl_rsp_payload_fragment_opcode <= factory_rsp_payload_fragment_opcode;
_zz_io_ctrl_rsp_payload_fragment_data <= factory_rsp_payload_fragment_data;
_zz_io_ctrl_rsp_payload_fragment_context <= factory_rsp_payload_fragment_context;
end
if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN) begin
mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind;
mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read;
mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write;
mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data;
end
if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin
mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind;
mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read;
mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write;
mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data;
end
case(io_ctrl_cmd_payload_fragment_address)
12'h008 : begin
if(factory_doWrite) begin
_zz_io_config_kind_cpol <= _zz_io_config_kind_cpol_1[0];
_zz_io_config_kind_cpha <= _zz_io_config_kind_cpol_1[1];
_zz_io_config_mod <= io_ctrl_cmd_payload_fragment_data[5 : 4];
end
end
12'h020 : begin
if(factory_doWrite) begin
_zz_io_config_sclkToggle <= io_ctrl_cmd_payload_fragment_data[11 : 0];
end
end
12'h024 : begin
if(factory_doWrite) begin
_zz_io_config_ss_setup <= io_ctrl_cmd_payload_fragment_data[11 : 0];
end
end
12'h028 : begin
if(factory_doWrite) begin
_zz_io_config_ss_hold <= io_ctrl_cmd_payload_fragment_data[11 : 0];
end
end
12'h02c : begin
if(factory_doWrite) begin
_zz_io_config_ss_disable <= io_ctrl_cmd_payload_fragment_data[11 : 0];
end
end
default : begin
end
endcase
end
endmodule
module Axi4PeripheralBmbUartCtrl_86b7e1c47b934a8a97a62bda8ee6a75d (
input wire io_bus_cmd_valid,
output wire io_bus_cmd_ready,
input wire io_bus_cmd_payload_last,
input wire [0:0] io_bus_cmd_payload_fragment_opcode,
input wire [5:0] io_bus_cmd_payload_fragment_address,
input wire [1:0] io_bus_cmd_payload_fragment_length,
input wire [31:0] io_bus_cmd_payload_fragment_data,
input wire [2:0] io_bus_cmd_payload_fragment_context,
output wire io_bus_rsp_valid,
input wire io_bus_rsp_ready,
output wire io_bus_rsp_payload_last,
output wire [0:0] io_bus_rsp_payload_fragment_opcode,
output wire [31:0] io_bus_rsp_payload_fragment_data,
output wire [2:0] io_bus_rsp_payload_fragment_context,
output wire io_uart_txd,
input wire io_uart_rxd,
output wire system_uart_0_io_interrupt_source,
input wire clk,
input wire reset
);
localparam Axi4PeripheralUartStopType_ONE = 1'd0;
localparam Axi4PeripheralUartStopType_TWO = 1'd1;
localparam Axi4PeripheralUartParityType_NONE = 2'd0;
localparam Axi4PeripheralUartParityType_EVEN = 2'd1;
localparam Axi4PeripheralUartParityType_ODD = 2'd2;
reg uartCtrl_io_read_queueWithOccupancy_io_pop_ready;
wire uartCtrl_io_write_ready;
wire uartCtrl_io_read_valid;
wire [7:0] uartCtrl_io_read_payload;
wire uartCtrl_io_uart_txd;
wire uartCtrl_io_readError;
wire uartCtrl_io_readBreak;
wire bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready;
wire bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid;
wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload;
wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy;
wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_availability;
wire uartCtrl_io_read_queueWithOccupancy_io_push_ready;
wire uartCtrl_io_read_queueWithOccupancy_io_pop_valid;
wire [7:0] uartCtrl_io_read_queueWithOccupancy_io_pop_payload;
wire [7:0] uartCtrl_io_read_queueWithOccupancy_io_occupancy;
wire [7:0] uartCtrl_io_read_queueWithOccupancy_io_availability;
wire [0:0] _zz_bridge_misc_readError;
wire [0:0] _zz_bridge_misc_readOverflowError;
wire [0:0] _zz_bridge_misc_breakDetected;
wire [0:0] _zz_bridge_misc_doBreak;
wire [0:0] _zz_bridge_misc_doBreak_1;
wire [7:0] _zz_busCtrl_rsp_payload_fragment_data;
wire busCtrl_readErrorFlag;
wire busCtrl_writeErrorFlag;
wire busCtrl_readHaltTrigger;
wire busCtrl_writeHaltTrigger;
wire busCtrl_rsp_valid;
wire busCtrl_rsp_ready;
wire busCtrl_rsp_payload_last;
reg [0:0] busCtrl_rsp_payload_fragment_opcode;
reg [31:0] busCtrl_rsp_payload_fragment_data;
wire [2:0] busCtrl_rsp_payload_fragment_context;
wire _zz_busCtrl_rsp_ready;
reg _zz_busCtrl_rsp_ready_1;
wire _zz_io_bus_rsp_valid;
reg _zz_io_bus_rsp_valid_1;
reg _zz_io_bus_rsp_payload_last;
reg [0:0] _zz_io_bus_rsp_payload_fragment_opcode;
reg [31:0] _zz_io_bus_rsp_payload_fragment_data;
reg [2:0] _zz_io_bus_rsp_payload_fragment_context;
wire when_Stream_l375;
wire busCtrl_askWrite;
wire busCtrl_askRead;
wire io_bus_cmd_fire;
wire busCtrl_doWrite;
wire busCtrl_doRead;
wire when_BmbSlaveFactory_l33;
wire when_BmbSlaveFactory_l35;
wire bridge_busCtrlWrapped_readErrorFlag;
wire bridge_busCtrlWrapped_writeErrorFlag;
reg [2:0] bridge_uartConfigReg_frame_dataLength;
reg [0:0] bridge_uartConfigReg_frame_stop;
reg [1:0] bridge_uartConfigReg_frame_parity;
reg [19:0] bridge_uartConfigReg_clockDivider;
reg _zz_bridge_write_streamUnbuffered_valid;
wire bridge_write_streamUnbuffered_valid;
wire bridge_write_streamUnbuffered_ready;
wire [7:0] bridge_write_streamUnbuffered_payload;
reg bridge_read_streamBreaked_valid;
reg bridge_read_streamBreaked_ready;
wire [7:0] bridge_read_streamBreaked_payload;
reg bridge_interruptCtrl_writeIntEnable;
reg bridge_interruptCtrl_readIntEnable;
wire bridge_interruptCtrl_readInt;
wire bridge_interruptCtrl_writeInt;
wire bridge_interruptCtrl_interrupt;
reg bridge_misc_readError;
reg when_BusSlaveFactory_l341;
wire when_BusSlaveFactory_l347;
reg bridge_misc_readOverflowError;
reg when_BusSlaveFactory_l341_1;
wire when_BusSlaveFactory_l347_1;
wire uartCtrl_io_read_isStall;
reg bridge_misc_breakDetected;
reg uartCtrl_io_readBreak_regNext;
wire when_UartCtrl_l155;
reg when_BusSlaveFactory_l341_2;
wire when_BusSlaveFactory_l347_2;
reg bridge_misc_doBreak;
reg when_BusSlaveFactory_l377;
wire when_BusSlaveFactory_l379;
reg when_BusSlaveFactory_l341_3;
wire when_BusSlaveFactory_l347_3;
wire [1:0] _zz_bridge_uartConfigReg_frame_parity;
wire [0:0] _zz_bridge_uartConfigReg_frame_stop;
wire when_BmbSlaveFactory_l77;
`ifndef SYNTHESIS
reg [23:0] bridge_uartConfigReg_frame_stop_string;
reg [31:0] bridge_uartConfigReg_frame_parity_string;
reg [31:0] _zz_bridge_uartConfigReg_frame_parity_string;
reg [23:0] _zz_bridge_uartConfigReg_frame_stop_string;
`endif
assign _zz_bridge_misc_readError = 1'b0;
assign _zz_bridge_misc_readOverflowError = 1'b0;
assign _zz_bridge_misc_breakDetected = 1'b0;
assign _zz_bridge_misc_doBreak = 1'b1;
assign _zz_bridge_misc_doBreak_1 = 1'b0;
assign _zz_busCtrl_rsp_payload_fragment_data = (8'h80 - bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy);
Axi4PeripheralUartCtrl_86b7e1c47b934a8a97a62bda8ee6a75d uartCtrl (
.io_config_frame_dataLength (bridge_uartConfigReg_frame_dataLength[2:0] ), //i
.io_config_frame_stop (bridge_uartConfigReg_frame_stop ), //i
.io_config_frame_parity (bridge_uartConfigReg_frame_parity[1:0] ), //i
.io_config_clockDivider (bridge_uartConfigReg_clockDivider[19:0] ), //i
.io_write_valid (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid ), //i
.io_write_ready (uartCtrl_io_write_ready ), //o
.io_write_payload (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload[7:0]), //i
.io_read_valid (uartCtrl_io_read_valid ), //o
.io_read_ready (uartCtrl_io_read_queueWithOccupancy_io_push_ready ), //i
.io_read_payload (uartCtrl_io_read_payload[7:0] ), //o
.io_uart_txd (uartCtrl_io_uart_txd ), //o
.io_uart_rxd (io_uart_rxd ), //i
.io_readError (uartCtrl_io_readError ), //o
.io_writeBreak (bridge_misc_doBreak ), //i
.io_readBreak (uartCtrl_io_readBreak ), //o
.clk (clk ), //i
.reset (reset ) //i
);
Axi4PeripheralStreamFifo_86b7e1c47b934a8a97a62bda8ee6a75d bridge_write_streamUnbuffered_queueWithOccupancy (
.io_push_valid (bridge_write_streamUnbuffered_valid ), //i
.io_push_ready (bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready ), //o
.io_push_payload (bridge_write_streamUnbuffered_payload[7:0] ), //i
.io_pop_valid (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid ), //o
.io_pop_ready (uartCtrl_io_write_ready ), //i
.io_pop_payload (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload[7:0] ), //o
.io_flush (1'b0 ), //i
.io_occupancy (bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy[7:0] ), //o
.io_availability (bridge_write_streamUnbuffered_queueWithOccupancy_io_availability[7:0]), //o
.clk (clk ), //i
.reset (reset ) //i
);
Axi4PeripheralStreamFifo_86b7e1c47b934a8a97a62bda8ee6a75d uartCtrl_io_read_queueWithOccupancy (
.io_push_valid (uartCtrl_io_read_valid ), //i
.io_push_ready (uartCtrl_io_read_queueWithOccupancy_io_push_ready ), //o
.io_push_payload (uartCtrl_io_read_payload[7:0] ), //i
.io_pop_valid (uartCtrl_io_read_queueWithOccupancy_io_pop_valid ), //o
.io_pop_ready (uartCtrl_io_read_queueWithOccupancy_io_pop_ready ), //i
.io_pop_payload (uartCtrl_io_read_queueWithOccupancy_io_pop_payload[7:0] ), //o
.io_flush (1'b0 ), //i
.io_occupancy (uartCtrl_io_read_queueWithOccupancy_io_occupancy[7:0] ), //o
.io_availability (uartCtrl_io_read_queueWithOccupancy_io_availability[7:0]), //o
.clk (clk ), //i
.reset (reset ) //i
);
`ifndef SYNTHESIS
always @(*) begin
case(bridge_uartConfigReg_frame_stop)
Axi4PeripheralUartStopType_ONE : bridge_uartConfigReg_frame_stop_string = "ONE";
Axi4PeripheralUartStopType_TWO : bridge_uartConfigReg_frame_stop_string = "TWO";
default : bridge_uartConfigReg_frame_stop_string = "???";
endcase
end
always @(*) begin
case(bridge_uartConfigReg_frame_parity)
Axi4PeripheralUartParityType_NONE : bridge_uartConfigReg_frame_parity_string = "NONE";
Axi4PeripheralUartParityType_EVEN : bridge_uartConfigReg_frame_parity_string = "EVEN";
Axi4PeripheralUartParityType_ODD : bridge_uartConfigReg_frame_parity_string = "ODD ";
default : bridge_uartConfigReg_frame_parity_string = "????";
endcase
end
always @(*) begin
case(_zz_bridge_uartConfigReg_frame_parity)
Axi4PeripheralUartParityType_NONE : _zz_bridge_uartConfigReg_frame_parity_string = "NONE";
Axi4PeripheralUartParityType_EVEN : _zz_bridge_uartConfigReg_frame_parity_string = "EVEN";
Axi4PeripheralUartParityType_ODD : _zz_bridge_uartConfigReg_frame_parity_string = "ODD ";
default : _zz_bridge_uartConfigReg_frame_parity_string = "????";
endcase
end
always @(*) begin
case(_zz_bridge_uartConfigReg_frame_stop)
Axi4PeripheralUartStopType_ONE : _zz_bridge_uartConfigReg_frame_stop_string = "ONE";
Axi4PeripheralUartStopType_TWO : _zz_bridge_uartConfigReg_frame_stop_string = "TWO";
default : _zz_bridge_uartConfigReg_frame_stop_string = "???";
endcase
end
`endif
assign io_uart_txd = uartCtrl_io_uart_txd;
assign busCtrl_readErrorFlag = 1'b0;
assign busCtrl_writeErrorFlag = 1'b0;
assign busCtrl_readHaltTrigger = 1'b0;
assign busCtrl_writeHaltTrigger = 1'b0;
assign _zz_busCtrl_rsp_ready = (! (busCtrl_readHaltTrigger || busCtrl_writeHaltTrigger));
assign busCtrl_rsp_ready = (_zz_busCtrl_rsp_ready_1 && _zz_busCtrl_rsp_ready);
always @(*) begin
_zz_busCtrl_rsp_ready_1 = io_bus_rsp_ready;
if(when_Stream_l375) begin
_zz_busCtrl_rsp_ready_1 = 1'b1;
end
end
assign when_Stream_l375 = (! _zz_io_bus_rsp_valid);
assign _zz_io_bus_rsp_valid = _zz_io_bus_rsp_valid_1;
assign io_bus_rsp_valid = _zz_io_bus_rsp_valid;
assign io_bus_rsp_payload_last = _zz_io_bus_rsp_payload_last;
assign io_bus_rsp_payload_fragment_opcode = _zz_io_bus_rsp_payload_fragment_opcode;
assign io_bus_rsp_payload_fragment_data = _zz_io_bus_rsp_payload_fragment_data;
assign io_bus_rsp_payload_fragment_context = _zz_io_bus_rsp_payload_fragment_context;
assign busCtrl_askWrite = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b1));
assign busCtrl_askRead = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b0));
assign io_bus_cmd_fire = (io_bus_cmd_valid && io_bus_cmd_ready);
assign busCtrl_doWrite = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b1));
assign busCtrl_doRead = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b0));
assign busCtrl_rsp_valid = io_bus_cmd_valid;
assign io_bus_cmd_ready = busCtrl_rsp_ready;
assign busCtrl_rsp_payload_last = 1'b1;
assign when_BmbSlaveFactory_l33 = (busCtrl_doWrite && busCtrl_writeErrorFlag);
always @(*) begin
if(when_BmbSlaveFactory_l33) begin
busCtrl_rsp_payload_fragment_opcode = 1'b1;
end else begin
if(when_BmbSlaveFactory_l35) begin
busCtrl_rsp_payload_fragment_opcode = 1'b1;
end else begin
busCtrl_rsp_payload_fragment_opcode = 1'b0;
end
end
end
assign when_BmbSlaveFactory_l35 = (busCtrl_doRead && busCtrl_readErrorFlag);
always @(*) begin
busCtrl_rsp_payload_fragment_data = 32'h0;
case(io_bus_cmd_payload_fragment_address)
6'h0 : begin
busCtrl_rsp_payload_fragment_data[16 : 16] = (bridge_read_streamBreaked_valid ^ 1'b0);
busCtrl_rsp_payload_fragment_data[7 : 0] = bridge_read_streamBreaked_payload;
end
6'h04 : begin
busCtrl_rsp_payload_fragment_data[23 : 16] = _zz_busCtrl_rsp_payload_fragment_data;
busCtrl_rsp_payload_fragment_data[15 : 15] = bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid;
busCtrl_rsp_payload_fragment_data[31 : 24] = uartCtrl_io_read_queueWithOccupancy_io_occupancy;
busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_interruptCtrl_writeIntEnable;
busCtrl_rsp_payload_fragment_data[1 : 1] = bridge_interruptCtrl_readIntEnable;
busCtrl_rsp_payload_fragment_data[8 : 8] = bridge_interruptCtrl_writeInt;
busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_interruptCtrl_readInt;
end
6'h10 : begin
busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_misc_readError;
busCtrl_rsp_payload_fragment_data[1 : 1] = bridge_misc_readOverflowError;
busCtrl_rsp_payload_fragment_data[8 : 8] = uartCtrl_io_readBreak;
busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_misc_breakDetected;
end
default : begin
end
endcase
end
assign busCtrl_rsp_payload_fragment_context = io_bus_cmd_payload_fragment_context;
assign bridge_busCtrlWrapped_readErrorFlag = 1'b0;
assign bridge_busCtrlWrapped_writeErrorFlag = 1'b0;
always @(*) begin
_zz_bridge_write_streamUnbuffered_valid = 1'b0;
case(io_bus_cmd_payload_fragment_address)
6'h0 : begin
if(busCtrl_doWrite) begin
_zz_bridge_write_streamUnbuffered_valid = 1'b1;
end
end
default : begin
end
endcase
end
assign bridge_write_streamUnbuffered_valid = _zz_bridge_write_streamUnbuffered_valid;
assign bridge_write_streamUnbuffered_payload = io_bus_cmd_payload_fragment_data[7 : 0];
assign bridge_write_streamUnbuffered_ready = bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready;
always @(*) begin
bridge_read_streamBreaked_valid = uartCtrl_io_read_queueWithOccupancy_io_pop_valid;
if(uartCtrl_io_readBreak) begin
bridge_read_streamBreaked_valid = 1'b0;
end
end
always @(*) begin
uartCtrl_io_read_queueWithOccupancy_io_pop_ready = bridge_read_streamBreaked_ready;
if(uartCtrl_io_readBreak) begin
uartCtrl_io_read_queueWithOccupancy_io_pop_ready = 1'b1;
end
end
assign bridge_read_streamBreaked_payload = uartCtrl_io_read_queueWithOccupancy_io_pop_payload;
always @(*) begin
bridge_read_streamBreaked_ready = 1'b0;
case(io_bus_cmd_payload_fragment_address)
6'h0 : begin
if(busCtrl_doRead) begin
bridge_read_streamBreaked_ready = 1'b1;
end
end
default : begin
end
endcase
end
assign bridge_interruptCtrl_readInt = (bridge_interruptCtrl_readIntEnable && bridge_read_streamBreaked_valid);
assign bridge_interruptCtrl_writeInt = (bridge_interruptCtrl_writeIntEnable && (! bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid));
assign bridge_interruptCtrl_interrupt = (bridge_interruptCtrl_readInt || bridge_interruptCtrl_writeInt);
always @(*) begin
when_BusSlaveFactory_l341 = 1'b0;
case(io_bus_cmd_payload_fragment_address)
6'h10 : begin
if(busCtrl_doWrite) begin
when_BusSlaveFactory_l341 = 1'b1;
end
end
default : begin
end
endcase
end
assign when_BusSlaveFactory_l347 = io_bus_cmd_payload_fragment_data[0];
always @(*) begin
when_BusSlaveFactory_l341_1 = 1'b0;
case(io_bus_cmd_payload_fragment_address)
6'h10 : begin
if(busCtrl_doWrite) begin
when_BusSlaveFactory_l341_1 = 1'b1;
end
end
default : begin
end
endcase
end
assign when_BusSlaveFactory_l347_1 = io_bus_cmd_payload_fragment_data[1];
assign uartCtrl_io_read_isStall = (uartCtrl_io_read_valid && (! uartCtrl_io_read_queueWithOccupancy_io_push_ready));
assign when_UartCtrl_l155 = (uartCtrl_io_readBreak && (! uartCtrl_io_readBreak_regNext));
always @(*) begin
when_BusSlaveFactory_l341_2 = 1'b0;
case(io_bus_cmd_payload_fragment_address)
6'h10 : begin
if(busCtrl_doWrite) begin
when_BusSlaveFactory_l341_2 = 1'b1;
end
end
default : begin
end
endcase
end
assign when_BusSlaveFactory_l347_2 = io_bus_cmd_payload_fragment_data[9];
always @(*) begin
when_BusSlaveFactory_l377 = 1'b0;
case(io_bus_cmd_payload_fragment_address)
6'h10 : begin
if(busCtrl_doWrite) begin
when_BusSlaveFactory_l377 = 1'b1;
end
end
default : begin
end
endcase
end
assign when_BusSlaveFactory_l379 = io_bus_cmd_payload_fragment_data[10];
always @(*) begin
when_BusSlaveFactory_l341_3 = 1'b0;
case(io_bus_cmd_payload_fragment_address)
6'h10 : begin
if(busCtrl_doWrite) begin
when_BusSlaveFactory_l341_3 = 1'b1;
end
end
default : begin
end
endcase
end
assign when_BusSlaveFactory_l347_3 = io_bus_cmd_payload_fragment_data[11];
assign system_uart_0_io_interrupt_source = bridge_interruptCtrl_interrupt;
assign _zz_bridge_uartConfigReg_frame_parity = io_bus_cmd_payload_fragment_data[9 : 8];
assign _zz_bridge_uartConfigReg_frame_stop = io_bus_cmd_payload_fragment_data[16 : 16];
assign when_BmbSlaveFactory_l77 = ((io_bus_cmd_payload_fragment_address & (~ 6'h03)) == 6'h08);
always @(posedge clk) begin
if(reset) begin
_zz_io_bus_rsp_valid_1 <= 1'b0;
bridge_uartConfigReg_clockDivider <= 20'h0;
bridge_uartConfigReg_clockDivider <= 20'h0010e;
bridge_uartConfigReg_frame_dataLength <= 3'b111;
bridge_uartConfigReg_frame_parity <= Axi4PeripheralUartParityType_NONE;
bridge_uartConfigReg_frame_stop <= Axi4PeripheralUartStopType_ONE;
bridge_interruptCtrl_writeIntEnable <= 1'b0;
bridge_interruptCtrl_readIntEnable <= 1'b0;
bridge_misc_readError <= 1'b0;
bridge_misc_readOverflowError <= 1'b0;
bridge_misc_breakDetected <= 1'b0;
bridge_misc_doBreak <= 1'b0;
end else begin
if(_zz_busCtrl_rsp_ready_1) begin
_zz_io_bus_rsp_valid_1 <= (busCtrl_rsp_valid && _zz_busCtrl_rsp_ready);
end
if(when_BusSlaveFactory_l341) begin
if(when_BusSlaveFactory_l347) begin
bridge_misc_readError <= _zz_bridge_misc_readError[0];
end
end
if(uartCtrl_io_readError) begin
bridge_misc_readError <= 1'b1;
end
if(when_BusSlaveFactory_l341_1) begin
if(when_BusSlaveFactory_l347_1) begin
bridge_misc_readOverflowError <= _zz_bridge_misc_readOverflowError[0];
end
end
if(uartCtrl_io_read_isStall) begin
bridge_misc_readOverflowError <= 1'b1;
end
if(when_UartCtrl_l155) begin
bridge_misc_breakDetected <= 1'b1;
end
if(when_BusSlaveFactory_l341_2) begin
if(when_BusSlaveFactory_l347_2) begin
bridge_misc_breakDetected <= _zz_bridge_misc_breakDetected[0];
end
end
if(when_BusSlaveFactory_l377) begin
if(when_BusSlaveFactory_l379) begin
bridge_misc_doBreak <= _zz_bridge_misc_doBreak[0];
end
end
if(when_BusSlaveFactory_l341_3) begin
if(when_BusSlaveFactory_l347_3) begin
bridge_misc_doBreak <= _zz_bridge_misc_doBreak_1[0];
end
end
case(io_bus_cmd_payload_fragment_address)
6'h0c : begin
if(busCtrl_doWrite) begin
bridge_uartConfigReg_frame_dataLength <= io_bus_cmd_payload_fragment_data[2 : 0];
bridge_uartConfigReg_frame_parity <= _zz_bridge_uartConfigReg_frame_parity;
bridge_uartConfigReg_frame_stop <= _zz_bridge_uartConfigReg_frame_stop;
end
end
6'h04 : begin
if(busCtrl_doWrite) begin
bridge_interruptCtrl_writeIntEnable <= io_bus_cmd_payload_fragment_data[0];
bridge_interruptCtrl_readIntEnable <= io_bus_cmd_payload_fragment_data[1];
end
end
default : begin
end
endcase
if(when_BmbSlaveFactory_l77) begin
if(busCtrl_doWrite) begin
bridge_uartConfigReg_clockDivider[19 : 0] <= io_bus_cmd_payload_fragment_data[19 : 0];
end
end
end
end
always @(posedge clk) begin
if(_zz_busCtrl_rsp_ready_1) begin
_zz_io_bus_rsp_payload_last <= busCtrl_rsp_payload_last;
_zz_io_bus_rsp_payload_fragment_opcode <= busCtrl_rsp_payload_fragment_opcode;
_zz_io_bus_rsp_payload_fragment_data <= busCtrl_rsp_payload_fragment_data;
_zz_io_bus_rsp_payload_fragment_context <= busCtrl_rsp_payload_fragment_context;
end
uartCtrl_io_readBreak_regNext <= uartCtrl_io_readBreak;
end
endmodule
module Axi4PeripheralBmbDecoder_1_86b7e1c47b934a8a97a62bda8ee6a75d (
input wire io_input_cmd_valid,
output wire io_input_cmd_ready,
input wire io_input_cmd_payload_last,
input wire [0:0] io_input_cmd_payload_fragment_opcode,
input wire [23:0] io_input_cmd_payload_fragment_address,
input wire [1:0] io_input_cmd_payload_fragment_length,
input wire [31:0] io_input_cmd_payload_fragment_data,
input wire [3:0] io_input_cmd_payload_fragment_mask,
input wire [2:0] io_input_cmd_payload_fragment_context,
output reg io_input_rsp_valid,
input wire io_input_rsp_ready,
output reg io_input_rsp_payload_last,
output reg [0:0] io_input_rsp_payload_fragment_opcode,
output wire [31:0] io_input_rsp_payload_fragment_data,
output reg [2:0] io_input_rsp_payload_fragment_context,
output reg io_outputs_0_cmd_valid,
input wire io_outputs_0_cmd_ready,
output wire io_outputs_0_cmd_payload_last,
output wire [0:0] io_outputs_0_cmd_payload_fragment_opcode,
output wire [23:0] io_outputs_0_cmd_payload_fragment_address,
output wire [1:0] io_outputs_0_cmd_payload_fragment_length,
output wire [31:0] io_outputs_0_cmd_payload_fragment_data,
output wire [3:0] io_outputs_0_cmd_payload_fragment_mask,
output wire [2:0] io_outputs_0_cmd_payload_fragment_context,
input wire io_outputs_0_rsp_valid,
output wire io_outputs_0_rsp_ready,
input wire io_outputs_0_rsp_payload_last,
input wire [0:0] io_outputs_0_rsp_payload_fragment_opcode,
input wire [31:0] io_outputs_0_rsp_payload_fragment_data,
input wire [2:0] io_outputs_0_rsp_payload_fragment_context,
output reg io_outputs_1_cmd_valid,
input wire io_outputs_1_cmd_ready,
output wire io_outputs_1_cmd_payload_last,
output wire [0:0] io_outputs_1_cmd_payload_fragment_opcode,
output wire [23:0] io_outputs_1_cmd_payload_fragment_address,
output wire [1:0] io_outputs_1_cmd_payload_fragment_length,
output wire [31:0] io_outputs_1_cmd_payload_fragment_data,
output wire [3:0] io_outputs_1_cmd_payload_fragment_mask,
output wire [2:0] io_outputs_1_cmd_payload_fragment_context,
input wire io_outputs_1_rsp_valid,
output wire io_outputs_1_rsp_ready,
input wire io_outputs_1_rsp_payload_last,
input wire [0:0] io_outputs_1_rsp_payload_fragment_opcode,
input wire [31:0] io_outputs_1_rsp_payload_fragment_data,
input wire [2:0] io_outputs_1_rsp_payload_fragment_context,
input wire clk,
input wire reset
);
wire [6:0] _zz_logic_rspPendingCounter;
wire [6:0] _zz_logic_rspPendingCounter_1;
wire [0:0] _zz_logic_rspPendingCounter_2;
wire [6:0] _zz_logic_rspPendingCounter_3;
wire [0:0] _zz_logic_rspPendingCounter_4;
reg _zz_io_input_rsp_payload_last_1;
reg [0:0] _zz_io_input_rsp_payload_fragment_opcode;
reg [31:0] _zz_io_input_rsp_payload_fragment_data;
reg [2:0] _zz_io_input_rsp_payload_fragment_context;
wire logic_input_valid;
reg logic_input_ready;
wire logic_input_payload_last;
wire [0:0] logic_input_payload_fragment_opcode;
wire [23:0] logic_input_payload_fragment_address;
wire [1:0] logic_input_payload_fragment_length;
wire [31:0] logic_input_payload_fragment_data;
wire [3:0] logic_input_payload_fragment_mask;
wire [2:0] logic_input_payload_fragment_context;
wire logic_hitsS0_0;
wire logic_hitsS0_1;
wire logic_noHitS0;
wire _zz_io_outputs_0_cmd_payload_last;
wire _zz_io_outputs_1_cmd_payload_last;
reg [6:0] logic_rspPendingCounter;
wire logic_input_fire;
wire io_input_rsp_fire;
wire logic_cmdWait;
wire when_BmbDecoder_l56;
reg logic_rspHits_0;
reg logic_rspHits_1;
wire logic_rspPending;
wire logic_rspNoHitValid;
reg logic_rspNoHit_doIt;
wire when_BmbDecoder_l60;
wire when_BmbDecoder_l60_1;
reg logic_rspNoHit_singleBeatRsp;
reg [2:0] logic_rspNoHit_context;
wire [0:0] _zz_io_input_rsp_payload_last;
assign _zz_logic_rspPendingCounter = (logic_rspPendingCounter + _zz_logic_rspPendingCounter_1);
assign _zz_logic_rspPendingCounter_2 = (logic_input_fire && logic_input_payload_last);
assign _zz_logic_rspPendingCounter_1 = {6'd0, _zz_logic_rspPendingCounter_2};
assign _zz_logic_rspPendingCounter_4 = (io_input_rsp_fire && io_input_rsp_payload_last);
assign _zz_logic_rspPendingCounter_3 = {6'd0, _zz_logic_rspPendingCounter_4};
always @(*) begin
case(_zz_io_input_rsp_payload_last)
1'b0 : begin
_zz_io_input_rsp_payload_last_1 = io_outputs_0_rsp_payload_last;
_zz_io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode;
_zz_io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data;
_zz_io_input_rsp_payload_fragment_context = io_outputs_0_rsp_payload_fragment_context;
end
default : begin
_zz_io_input_rsp_payload_last_1 = io_outputs_1_rsp_payload_last;
_zz_io_input_rsp_payload_fragment_opcode = io_outputs_1_rsp_payload_fragment_opcode;
_zz_io_input_rsp_payload_fragment_data = io_outputs_1_rsp_payload_fragment_data;
_zz_io_input_rsp_payload_fragment_context = io_outputs_1_rsp_payload_fragment_context;
end
endcase
end
assign logic_input_valid = io_input_cmd_valid;
assign io_input_cmd_ready = logic_input_ready;
assign logic_input_payload_last = io_input_cmd_payload_last;
assign logic_input_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode;
assign logic_input_payload_fragment_address = io_input_cmd_payload_fragment_address;
assign logic_input_payload_fragment_length = io_input_cmd_payload_fragment_length;
assign logic_input_payload_fragment_data = io_input_cmd_payload_fragment_data;
assign logic_input_payload_fragment_mask = io_input_cmd_payload_fragment_mask;
assign logic_input_payload_fragment_context = io_input_cmd_payload_fragment_context;
assign logic_noHitS0 = (! (|{logic_hitsS0_1,logic_hitsS0_0}));
assign logic_hitsS0_0 = ((io_input_cmd_payload_fragment_address & (~ 24'h00003f)) == 24'h010000);
always @(*) begin
io_outputs_0_cmd_valid = (logic_input_valid && logic_hitsS0_0);
if(logic_cmdWait) begin
io_outputs_0_cmd_valid = 1'b0;
end
end
assign _zz_io_outputs_0_cmd_payload_last = logic_input_payload_last;
assign io_outputs_0_cmd_payload_last = _zz_io_outputs_0_cmd_payload_last;
assign io_outputs_0_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode;
assign io_outputs_0_cmd_payload_fragment_address = logic_input_payload_fragment_address;
assign io_outputs_0_cmd_payload_fragment_length = logic_input_payload_fragment_length;
assign io_outputs_0_cmd_payload_fragment_data = logic_input_payload_fragment_data;
assign io_outputs_0_cmd_payload_fragment_mask = logic_input_payload_fragment_mask;
assign io_outputs_0_cmd_payload_fragment_context = logic_input_payload_fragment_context;
assign logic_hitsS0_1 = ((io_input_cmd_payload_fragment_address & (~ 24'h000fff)) == 24'h030000);
always @(*) begin
io_outputs_1_cmd_valid = (logic_input_valid && logic_hitsS0_1);
if(logic_cmdWait) begin
io_outputs_1_cmd_valid = 1'b0;
end
end
assign _zz_io_outputs_1_cmd_payload_last = logic_input_payload_last;
assign io_outputs_1_cmd_payload_last = _zz_io_outputs_1_cmd_payload_last;
assign io_outputs_1_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode;
assign io_outputs_1_cmd_payload_fragment_address = logic_input_payload_fragment_address;
assign io_outputs_1_cmd_payload_fragment_length = logic_input_payload_fragment_length;
assign io_outputs_1_cmd_payload_fragment_data = logic_input_payload_fragment_data;
assign io_outputs_1_cmd_payload_fragment_mask = logic_input_payload_fragment_mask;
assign io_outputs_1_cmd_payload_fragment_context = logic_input_payload_fragment_context;
always @(*) begin
logic_input_ready = ((|{(logic_hitsS0_1 && io_outputs_1_cmd_ready),(logic_hitsS0_0 && io_outputs_0_cmd_ready)}) || logic_noHitS0);
if(logic_cmdWait) begin
logic_input_ready = 1'b0;
end
end
assign logic_input_fire = (logic_input_valid && logic_input_ready);
assign io_input_rsp_fire = (io_input_rsp_valid && io_input_rsp_ready);
assign when_BmbDecoder_l56 = (logic_input_valid && (! logic_cmdWait));
assign logic_rspPending = (logic_rspPendingCounter != 7'h0);
assign logic_rspNoHitValid = (! (|{logic_rspHits_1,logic_rspHits_0}));
assign when_BmbDecoder_l60 = (io_input_rsp_fire && io_input_rsp_payload_last);
assign when_BmbDecoder_l60_1 = ((logic_input_fire && logic_noHitS0) && logic_input_payload_last);
always @(*) begin
io_input_rsp_valid = ((|{io_outputs_1_rsp_valid,io_outputs_0_rsp_valid}) || (logic_rspPending && logic_rspNoHitValid));
if(logic_rspNoHit_doIt) begin
io_input_rsp_valid = 1'b1;
end
end
assign _zz_io_input_rsp_payload_last = logic_rspHits_1;
always @(*) begin
io_input_rsp_payload_last = _zz_io_input_rsp_payload_last_1;
if(logic_rspNoHit_doIt) begin
io_input_rsp_payload_last = 1'b1;
end
end
always @(*) begin
io_input_rsp_payload_fragment_opcode = _zz_io_input_rsp_payload_fragment_opcode;
if(logic_rspNoHit_doIt) begin
io_input_rsp_payload_fragment_opcode = 1'b1;
end
end
assign io_input_rsp_payload_fragment_data = _zz_io_input_rsp_payload_fragment_data;
always @(*) begin
io_input_rsp_payload_fragment_context = _zz_io_input_rsp_payload_fragment_context;
if(logic_rspNoHit_doIt) begin
io_input_rsp_payload_fragment_context = logic_rspNoHit_context;
end
end
assign io_outputs_0_rsp_ready = io_input_rsp_ready;
assign io_outputs_1_rsp_ready = io_input_rsp_ready;
assign logic_cmdWait = ((logic_rspPending && (((logic_hitsS0_0 != logic_rspHits_0) || (logic_hitsS0_1 != logic_rspHits_1)) || logic_rspNoHitValid)) || (logic_rspPendingCounter == 7'h40));
always @(posedge clk) begin
if(reset) begin
logic_rspPendingCounter <= 7'h0;
logic_rspNoHit_doIt <= 1'b0;
end else begin
logic_rspPendingCounter <= (_zz_logic_rspPendingCounter - _zz_logic_rspPendingCounter_3);
if(when_BmbDecoder_l60) begin
logic_rspNoHit_doIt <= 1'b0;
end
if(when_BmbDecoder_l60_1) begin
logic_rspNoHit_doIt <= 1'b1;
end
end
end
always @(posedge clk) begin
if(when_BmbDecoder_l56) begin
logic_rspHits_0 <= logic_hitsS0_0;
logic_rspHits_1 <= logic_hitsS0_1;
end
if(logic_input_fire) begin
logic_rspNoHit_singleBeatRsp <= (logic_input_payload_fragment_opcode == 1'b1);
end
if(logic_input_fire) begin
logic_rspNoHit_context <= logic_input_payload_fragment_context;
end
end
endmodule
module Axi4PeripheralBmbUnburstify_86b7e1c47b934a8a97a62bda8ee6a75d (
input wire io_input_cmd_valid,
output reg io_input_cmd_ready,
input wire io_input_cmd_payload_last,
input wire [0:0] io_input_cmd_payload_fragment_source,
input wire [0:0] io_input_cmd_payload_fragment_opcode,
input wire [23:0] io_input_cmd_payload_fragment_address,
input wire [9:0] io_input_cmd_payload_fragment_length,
input wire [31:0] io_input_cmd_payload_fragment_data,
input wire [3:0] io_input_cmd_payload_fragment_mask,
output wire io_input_rsp_valid,
input wire io_input_rsp_ready,
output wire io_input_rsp_payload_last,
output wire [0:0] io_input_rsp_payload_fragment_source,
output wire [0:0] io_input_rsp_payload_fragment_opcode,
output wire [31:0] io_input_rsp_payload_fragment_data,
output reg io_output_cmd_valid,
input wire io_output_cmd_ready,
output wire io_output_cmd_payload_last,
output reg [0:0] io_output_cmd_payload_fragment_opcode,
output reg [23:0] io_output_cmd_payload_fragment_address,
output reg [1:0] io_output_cmd_payload_fragment_length,
output wire [31:0] io_output_cmd_payload_fragment_data,
output wire [3:0] io_output_cmd_payload_fragment_mask,
output wire [2:0] io_output_cmd_payload_fragment_context,
input wire io_output_rsp_valid,
output reg io_output_rsp_ready,
input wire io_output_rsp_payload_last,
input wire [0:0] io_output_rsp_payload_fragment_opcode,
input wire [31:0] io_output_rsp_payload_fragment_data,
input wire [2:0] io_output_rsp_payload_fragment_context,
input wire clk,
input wire reset
);
wire [7:0] _zz_buffer_last;
wire [0:0] _zz_buffer_last_1;
wire [11:0] _zz_buffer_addressIncr;
wire doResult;
reg buffer_valid;
reg [0:0] buffer_opcode;
reg [0:0] buffer_source;
reg [23:0] buffer_address;
reg [7:0] buffer_beat;
wire buffer_last;
wire [23:0] buffer_addressIncr;
wire buffer_isWrite;
wire io_output_cmd_fire;
wire [7:0] cmdTransferBeatCount;
wire requireBuffer;
reg cmdContext_drop;
reg cmdContext_last;
reg [0:0] cmdContext_source;
wire rspContext_drop;
wire rspContext_last;
wire [0:0] rspContext_source;
wire [2:0] _zz_rspContext_drop;
wire when_Stream_l445;
reg io_output_rsp_thrown_valid;
wire io_output_rsp_thrown_ready;
wire io_output_rsp_thrown_payload_last;
wire [0:0] io_output_rsp_thrown_payload_fragment_opcode;
wire [31:0] io_output_rsp_thrown_payload_fragment_data;
wire [2:0] io_output_rsp_thrown_payload_fragment_context;
assign _zz_buffer_last_1 = 1'b1;
assign _zz_buffer_last = {7'd0, _zz_buffer_last_1};
assign _zz_buffer_addressIncr = (buffer_address[11 : 0] + 12'h004);
assign buffer_last = (buffer_beat == _zz_buffer_last);
assign buffer_addressIncr = {buffer_address[23 : 12],(_zz_buffer_addressIncr & (~ 12'h003))};
assign buffer_isWrite = (buffer_opcode == 1'b1);
assign io_output_cmd_fire = (io_output_cmd_valid && io_output_cmd_ready);
assign cmdTransferBeatCount = io_input_cmd_payload_fragment_length[9 : 2];
assign requireBuffer = (cmdTransferBeatCount != 8'h0);
assign io_output_cmd_payload_fragment_data = io_input_cmd_payload_fragment_data;
assign io_output_cmd_payload_fragment_mask = io_input_cmd_payload_fragment_mask;
assign io_output_cmd_payload_last = 1'b1;
assign io_output_cmd_payload_fragment_context = {cmdContext_source,{cmdContext_last,cmdContext_drop}};
always @(*) begin
if(buffer_valid) begin
io_output_cmd_payload_fragment_address = buffer_addressIncr;
end else begin
io_output_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address;
if(requireBuffer) begin
io_output_cmd_payload_fragment_address[1 : 0] = 2'b00;
end
end
end
always @(*) begin
if(buffer_valid) begin
io_output_cmd_payload_fragment_opcode = buffer_opcode;
end else begin
io_output_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode;
end
end
always @(*) begin
if(buffer_valid) begin
io_output_cmd_payload_fragment_length = 2'b11;
end else begin
if(requireBuffer) begin
io_output_cmd_payload_fragment_length = 2'b11;
end else begin
io_output_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length[1:0];
end
end
end
always @(*) begin
if(buffer_valid) begin
cmdContext_source = buffer_source;
end else begin
cmdContext_source = io_input_cmd_payload_fragment_source;
end
end
always @(*) begin
io_input_cmd_ready = 1'b0;
if(buffer_valid) begin
io_input_cmd_ready = (buffer_isWrite && io_output_cmd_ready);
end else begin
io_input_cmd_ready = io_output_cmd_ready;
end
end
always @(*) begin
if(buffer_valid) begin
io_output_cmd_valid = (! (buffer_isWrite && (! io_input_cmd_valid)));
end else begin
io_output_cmd_valid = io_input_cmd_valid;
end
end
always @(*) begin
if(buffer_valid) begin
cmdContext_last = buffer_last;
end else begin
cmdContext_last = (! requireBuffer);
end
end
always @(*) begin
if(buffer_valid) begin
cmdContext_drop = buffer_isWrite;
end else begin
cmdContext_drop = (io_input_cmd_payload_fragment_opcode == 1'b1);
end
end
assign _zz_rspContext_drop = io_output_rsp_payload_fragment_context;
assign rspContext_drop = _zz_rspContext_drop[0];
assign rspContext_last = _zz_rspContext_drop[1];
assign rspContext_source = _zz_rspContext_drop[2 : 2];
assign when_Stream_l445 = (! (rspContext_last || (! rspContext_drop)));
always @(*) begin
io_output_rsp_thrown_valid = io_output_rsp_valid;
if(when_Stream_l445) begin
io_output_rsp_thrown_valid = 1'b0;
end
end
always @(*) begin
io_output_rsp_ready = io_output_rsp_thrown_ready;
if(when_Stream_l445) begin
io_output_rsp_ready = 1'b1;
end
end
assign io_output_rsp_thrown_payload_last = io_output_rsp_payload_last;
assign io_output_rsp_thrown_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode;
assign io_output_rsp_thrown_payload_fragment_data = io_output_rsp_payload_fragment_data;
assign io_output_rsp_thrown_payload_fragment_context = io_output_rsp_payload_fragment_context;
assign io_input_rsp_valid = io_output_rsp_thrown_valid;
assign io_output_rsp_thrown_ready = io_input_rsp_ready;
assign io_input_rsp_payload_last = rspContext_last;
assign io_input_rsp_payload_fragment_source = rspContext_source;
assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode;
assign io_input_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data;
always @(posedge clk) begin
if(reset) begin
buffer_valid <= 1'b0;
end else begin
if(io_output_cmd_fire) begin
if(buffer_last) begin
buffer_valid <= 1'b0;
end
end
if(!buffer_valid) begin
buffer_valid <= (requireBuffer && io_output_cmd_fire);
end
end
end
always @(posedge clk) begin
if(io_output_cmd_fire) begin
buffer_beat <= (buffer_beat - 8'h01);
buffer_address[11 : 0] <= buffer_addressIncr[11 : 0];
end
if(!buffer_valid) begin
buffer_opcode <= io_input_cmd_payload_fragment_opcode;
buffer_source <= io_input_cmd_payload_fragment_source;
buffer_address <= io_input_cmd_payload_fragment_address;
buffer_beat <= cmdTransferBeatCount;
end
end
endmodule
module Axi4PeripheralBmbDecoder_86b7e1c47b934a8a97a62bda8ee6a75d (
input wire io_input_cmd_valid,
output wire io_input_cmd_ready,
input wire io_input_cmd_payload_last,
input wire [0:0] io_input_cmd_payload_fragment_source,
input wire [0:0] io_input_cmd_payload_fragment_opcode,
input wire [23:0] io_input_cmd_payload_fragment_address,
input wire [9:0] io_input_cmd_payload_fragment_length,
input wire [31:0] io_input_cmd_payload_fragment_data,
input wire [3:0] io_input_cmd_payload_fragment_mask,
output reg io_input_rsp_valid,
input wire io_input_rsp_ready,
output reg io_input_rsp_payload_last,
output reg [0:0] io_input_rsp_payload_fragment_source,
output reg [0:0] io_input_rsp_payload_fragment_opcode,
output wire [31:0] io_input_rsp_payload_fragment_data,
output reg io_outputs_0_cmd_valid,
input wire io_outputs_0_cmd_ready,
output wire io_outputs_0_cmd_payload_last,
output wire [0:0] io_outputs_0_cmd_payload_fragment_source,
output wire [0:0] io_outputs_0_cmd_payload_fragment_opcode,
output wire [23:0] io_outputs_0_cmd_payload_fragment_address,
output wire [9:0] io_outputs_0_cmd_payload_fragment_length,
output wire [31:0] io_outputs_0_cmd_payload_fragment_data,
output wire [3:0] io_outputs_0_cmd_payload_fragment_mask,
input wire io_outputs_0_rsp_valid,
output wire io_outputs_0_rsp_ready,
input wire io_outputs_0_rsp_payload_last,
input wire [0:0] io_outputs_0_rsp_payload_fragment_source,
input wire [0:0] io_outputs_0_rsp_payload_fragment_opcode,
input wire [31:0] io_outputs_0_rsp_payload_fragment_data,
input wire clk,
input wire reset
);
wire [6:0] _zz_logic_rspPendingCounter;
wire [6:0] _zz_logic_rspPendingCounter_1;
wire [0:0] _zz_logic_rspPendingCounter_2;
wire [6:0] _zz_logic_rspPendingCounter_3;
wire [0:0] _zz_logic_rspPendingCounter_4;
wire logic_input_valid;
reg logic_input_ready;
wire logic_input_payload_last;
wire [0:0] logic_input_payload_fragment_source;
wire [0:0] logic_input_payload_fragment_opcode;
wire [23:0] logic_input_payload_fragment_address;
wire [9:0] logic_input_payload_fragment_length;
wire [31:0] logic_input_payload_fragment_data;
wire [3:0] logic_input_payload_fragment_mask;
wire logic_hitsS0_0;
wire logic_noHitS0;
wire _zz_io_outputs_0_cmd_payload_last;
reg [6:0] logic_rspPendingCounter;
wire logic_input_fire;
wire io_input_rsp_fire;
wire logic_cmdWait;
wire when_BmbDecoder_l56;
reg logic_rspHits_0;
wire logic_rspPending;
wire logic_rspNoHitValid;
reg logic_rspNoHit_doIt;
wire when_BmbDecoder_l60;
wire when_BmbDecoder_l60_1;
reg logic_rspNoHit_singleBeatRsp;
reg [0:0] logic_rspNoHit_source;
reg [7:0] logic_rspNoHit_counter;
wire when_BmbDecoder_l81;
assign _zz_logic_rspPendingCounter = (logic_rspPendingCounter + _zz_logic_rspPendingCounter_1);
assign _zz_logic_rspPendingCounter_2 = (logic_input_fire && logic_input_payload_last);
assign _zz_logic_rspPendingCounter_1 = {6'd0, _zz_logic_rspPendingCounter_2};
assign _zz_logic_rspPendingCounter_4 = (io_input_rsp_fire && io_input_rsp_payload_last);
assign _zz_logic_rspPendingCounter_3 = {6'd0, _zz_logic_rspPendingCounter_4};
assign logic_input_valid = io_input_cmd_valid;
assign io_input_cmd_ready = logic_input_ready;
assign logic_input_payload_last = io_input_cmd_payload_last;
assign logic_input_payload_fragment_source = io_input_cmd_payload_fragment_source;
assign logic_input_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode;
assign logic_input_payload_fragment_address = io_input_cmd_payload_fragment_address;
assign logic_input_payload_fragment_length = io_input_cmd_payload_fragment_length;
assign logic_input_payload_fragment_data = io_input_cmd_payload_fragment_data;
assign logic_input_payload_fragment_mask = io_input_cmd_payload_fragment_mask;
assign logic_noHitS0 = (! (|logic_hitsS0_0));
assign logic_hitsS0_0 = ((io_input_cmd_payload_fragment_address & (~ 24'hffffff)) == 24'h0);
always @(*) begin
io_outputs_0_cmd_valid = (logic_input_valid && logic_hitsS0_0);
if(logic_cmdWait) begin
io_outputs_0_cmd_valid = 1'b0;
end
end
assign _zz_io_outputs_0_cmd_payload_last = logic_input_payload_last;
assign io_outputs_0_cmd_payload_last = _zz_io_outputs_0_cmd_payload_last;
assign io_outputs_0_cmd_payload_fragment_source = logic_input_payload_fragment_source;
assign io_outputs_0_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode;
assign io_outputs_0_cmd_payload_fragment_address = logic_input_payload_fragment_address;
assign io_outputs_0_cmd_payload_fragment_length = logic_input_payload_fragment_length;
assign io_outputs_0_cmd_payload_fragment_data = logic_input_payload_fragment_data;
assign io_outputs_0_cmd_payload_fragment_mask = logic_input_payload_fragment_mask;
always @(*) begin
logic_input_ready = ((|(logic_hitsS0_0 && io_outputs_0_cmd_ready)) || logic_noHitS0);
if(logic_cmdWait) begin
logic_input_ready = 1'b0;
end
end
assign logic_input_fire = (logic_input_valid && logic_input_ready);
assign io_input_rsp_fire = (io_input_rsp_valid && io_input_rsp_ready);
assign when_BmbDecoder_l56 = (logic_input_valid && (! logic_cmdWait));
assign logic_rspPending = (logic_rspPendingCounter != 7'h0);
assign logic_rspNoHitValid = (! (|logic_rspHits_0));
assign when_BmbDecoder_l60 = (io_input_rsp_fire && io_input_rsp_payload_last);
assign when_BmbDecoder_l60_1 = ((logic_input_fire && logic_noHitS0) && logic_input_payload_last);
always @(*) begin
io_input_rsp_valid = ((|io_outputs_0_rsp_valid) || (logic_rspPending && logic_rspNoHitValid));
if(logic_rspNoHit_doIt) begin
io_input_rsp_valid = 1'b1;
end
end
always @(*) begin
io_input_rsp_payload_last = io_outputs_0_rsp_payload_last;
if(logic_rspNoHit_doIt) begin
io_input_rsp_payload_last = 1'b0;
if(when_BmbDecoder_l81) begin
io_input_rsp_payload_last = 1'b1;
end
if(logic_rspNoHit_singleBeatRsp) begin
io_input_rsp_payload_last = 1'b1;
end
end
end
always @(*) begin
io_input_rsp_payload_fragment_source = io_outputs_0_rsp_payload_fragment_source;
if(logic_rspNoHit_doIt) begin
io_input_rsp_payload_fragment_source = logic_rspNoHit_source;
end
end
always @(*) begin
io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode;
if(logic_rspNoHit_doIt) begin
io_input_rsp_payload_fragment_opcode = 1'b1;
end
end
assign io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data;
assign when_BmbDecoder_l81 = (logic_rspNoHit_counter == 8'h0);
assign io_outputs_0_rsp_ready = io_input_rsp_ready;
assign logic_cmdWait = ((logic_rspPending && ((logic_hitsS0_0 != logic_rspHits_0) || logic_rspNoHitValid)) || (logic_rspPendingCounter == 7'h40));
always @(posedge clk) begin
if(reset) begin
logic_rspPendingCounter <= 7'h0;
logic_rspNoHit_doIt <= 1'b0;
end else begin
logic_rspPendingCounter <= (_zz_logic_rspPendingCounter - _zz_logic_rspPendingCounter_3);
if(when_BmbDecoder_l60) begin
logic_rspNoHit_doIt <= 1'b0;
end
if(when_BmbDecoder_l60_1) begin
logic_rspNoHit_doIt <= 1'b1;
end
end
end
always @(posedge clk) begin
if(when_BmbDecoder_l56) begin
logic_rspHits_0 <= logic_hitsS0_0;
end
if(logic_input_fire) begin
logic_rspNoHit_singleBeatRsp <= (logic_input_payload_fragment_opcode == 1'b1);
end
if(logic_input_fire) begin
logic_rspNoHit_source <= logic_input_payload_fragment_source;
end
if(logic_input_fire) begin
logic_rspNoHit_counter <= logic_input_payload_fragment_length[9 : 2];
end
if(logic_rspNoHit_doIt) begin
if(io_input_rsp_fire) begin
logic_rspNoHit_counter <= (logic_rspNoHit_counter - 8'h01);
end
end
end
endmodule
module Axi4PeripheralAxi4SharedToBmb_86b7e1c47b934a8a97a62bda8ee6a75d (
input wire io_axi_arw_valid,
output wire io_axi_arw_ready,
input wire [23:0] io_axi_arw_payload_addr,
input wire [7:0] io_axi_arw_payload_len,
input wire [2:0] io_axi_arw_payload_size,
input wire [3:0] io_axi_arw_payload_cache,
input wire [2:0] io_axi_arw_payload_prot,
input wire io_axi_arw_payload_write,
input wire io_axi_w_valid,
output wire io_axi_w_ready,
input wire [31:0] io_axi_w_payload_data,
input wire [3:0] io_axi_w_payload_strb,
input wire io_axi_w_payload_last,
output wire io_axi_b_valid,
input wire io_axi_b_ready,
output reg [1:0] io_axi_b_payload_resp,
output wire io_axi_r_valid,
input wire io_axi_r_ready,
output wire [31:0] io_axi_r_payload_data,
output reg [1:0] io_axi_r_payload_resp,
output wire io_axi_r_payload_last,
output wire io_bmb_cmd_valid,
input wire io_bmb_cmd_ready,
output wire io_bmb_cmd_payload_last,
output wire [0:0] io_bmb_cmd_payload_fragment_source,
output wire [0:0] io_bmb_cmd_payload_fragment_opcode,
output wire [23:0] io_bmb_cmd_payload_fragment_address,
output wire [9:0] io_bmb_cmd_payload_fragment_length,
output wire [31:0] io_bmb_cmd_payload_fragment_data,
output wire [3:0] io_bmb_cmd_payload_fragment_mask,
input wire io_bmb_rsp_valid,
output wire io_bmb_rsp_ready,
input wire io_bmb_rsp_payload_last,
input wire [0:0] io_bmb_rsp_payload_fragment_source,
input wire [0:0] io_bmb_rsp_payload_fragment_opcode,
input wire [31:0] io_bmb_rsp_payload_fragment_data
);
wire [9:0] _zz_io_bmb_cmd_payload_fragment_length;
wire hazard;
wire io_bmb_cmd_fire;
wire rspIsWrite;
wire when_Axi4SharedToBmb_l42;
wire when_Axi4SharedToBmb_l49;
assign _zz_io_bmb_cmd_payload_fragment_length = ({2'd0,io_axi_arw_payload_len} <<< 2'd2);
assign hazard = (io_axi_arw_payload_write && (! io_axi_w_valid));
assign io_bmb_cmd_valid = (io_axi_arw_valid && (! hazard));
assign io_bmb_cmd_payload_fragment_source = io_axi_arw_payload_write;
assign io_bmb_cmd_payload_fragment_opcode = io_axi_arw_payload_write;
assign io_bmb_cmd_payload_fragment_address = io_axi_arw_payload_addr;
assign io_bmb_cmd_payload_fragment_length = (_zz_io_bmb_cmd_payload_fragment_length | 10'h003);
assign io_bmb_cmd_payload_fragment_data = io_axi_w_payload_data;
assign io_bmb_cmd_payload_fragment_mask = io_axi_w_payload_strb;
assign io_bmb_cmd_payload_last = ((! io_axi_arw_payload_write) || io_axi_w_payload_last);
assign io_bmb_cmd_fire = (io_bmb_cmd_valid && io_bmb_cmd_ready);
assign io_axi_arw_ready = (io_bmb_cmd_fire && io_bmb_cmd_payload_last);
assign io_axi_w_ready = (io_bmb_cmd_fire && (io_bmb_cmd_payload_fragment_opcode == 1'b1));
assign rspIsWrite = io_bmb_rsp_payload_fragment_source[0];
assign io_axi_b_valid = (io_bmb_rsp_valid && rspIsWrite);
always @(*) begin
io_axi_b_payload_resp = 2'b00;
if(when_Axi4SharedToBmb_l42) begin
io_axi_b_payload_resp = 2'b11;
end
end
assign when_Axi4SharedToBmb_l42 = (io_bmb_rsp_payload_fragment_opcode == 1'b1);
assign io_axi_r_valid = (io_bmb_rsp_valid && (! rspIsWrite));
assign io_axi_r_payload_data = io_bmb_rsp_payload_fragment_data;
assign io_axi_r_payload_last = io_bmb_rsp_payload_last;
always @(*) begin
io_axi_r_payload_resp = 2'b00;
if(when_Axi4SharedToBmb_l49) begin
io_axi_r_payload_resp = 2'b11;
end
end
assign when_Axi4SharedToBmb_l49 = (io_bmb_rsp_payload_fragment_opcode == 1'b1);
assign io_bmb_rsp_ready = (rspIsWrite ? io_axi_b_ready : io_axi_r_ready);
endmodule
module Axi4PeripheralStreamArbiter_86b7e1c47b934a8a97a62bda8ee6a75d (
input wire io_inputs_0_valid,
output wire io_inputs_0_ready,
input wire [23:0] io_inputs_0_payload_addr,
input wire [7:0] io_inputs_0_payload_len,
input wire [2:0] io_inputs_0_payload_size,
input wire [3:0] io_inputs_0_payload_cache,
input wire [2:0] io_inputs_0_payload_prot,
input wire io_inputs_1_valid,
output wire io_inputs_1_ready,
input wire [23:0] io_inputs_1_payload_addr,
input wire [7:0] io_inputs_1_payload_len,
input wire [2:0] io_inputs_1_payload_size,
input wire [3:0] io_inputs_1_payload_cache,
input wire [2:0] io_inputs_1_payload_prot,
output wire io_output_valid,
input wire io_output_ready,
output wire [23:0] io_output_payload_addr,
output wire [7:0] io_output_payload_len,
output wire [2:0] io_output_payload_size,
output wire [3:0] io_output_payload_cache,
output wire [2:0] io_output_payload_prot,
output wire [0:0] io_chosen,
output wire [1:0] io_chosenOH,
input wire clk,
input wire reset
);
wire [3:0] _zz__zz_maskProposal_0_2;
wire [3:0] _zz__zz_maskProposal_0_2_1;
wire [1:0] _zz__zz_maskProposal_0_2_2;
reg locked;
wire maskProposal_0;
wire maskProposal_1;
reg maskLocked_0;
reg maskLocked_1;
wire maskRouted_0;
wire maskRouted_1;
wire [1:0] _zz_maskProposal_0;
wire [3:0] _zz_maskProposal_0_1;
wire [3:0] _zz_maskProposal_0_2;
wire [1:0] _zz_maskProposal_0_3;
wire io_output_fire;
wire _zz_io_chosen;
assign _zz__zz_maskProposal_0_2 = (_zz_maskProposal_0_1 - _zz__zz_maskProposal_0_2_1);
assign _zz__zz_maskProposal_0_2_2 = {maskLocked_0,maskLocked_1};
assign _zz__zz_maskProposal_0_2_1 = {2'd0, _zz__zz_maskProposal_0_2_2};
assign maskRouted_0 = (locked ? maskLocked_0 : maskProposal_0);
assign maskRouted_1 = (locked ? maskLocked_1 : maskProposal_1);
assign _zz_maskProposal_0 = {io_inputs_1_valid,io_inputs_0_valid};
assign _zz_maskProposal_0_1 = {_zz_maskProposal_0,_zz_maskProposal_0};
assign _zz_maskProposal_0_2 = (_zz_maskProposal_0_1 & (~ _zz__zz_maskProposal_0_2));
assign _zz_maskProposal_0_3 = (_zz_maskProposal_0_2[3 : 2] | _zz_maskProposal_0_2[1 : 0]);
assign maskProposal_0 = _zz_maskProposal_0_3[0];
assign maskProposal_1 = _zz_maskProposal_0_3[1];
assign io_output_fire = (io_output_valid && io_output_ready);
assign io_output_valid = ((io_inputs_0_valid && maskRouted_0) || (io_inputs_1_valid && maskRouted_1));
assign io_output_payload_addr = (maskRouted_0 ? io_inputs_0_payload_addr : io_inputs_1_payload_addr);
assign io_output_payload_len = (maskRouted_0 ? io_inputs_0_payload_len : io_inputs_1_payload_len);
assign io_output_payload_size = (maskRouted_0 ? io_inputs_0_payload_size : io_inputs_1_payload_size);
assign io_output_payload_cache = (maskRouted_0 ? io_inputs_0_payload_cache : io_inputs_1_payload_cache);
assign io_output_payload_prot = (maskRouted_0 ? io_inputs_0_payload_prot : io_inputs_1_payload_prot);
assign io_inputs_0_ready = (maskRouted_0 && io_output_ready);
assign io_inputs_1_ready = (maskRouted_1 && io_output_ready);
assign io_chosenOH = {maskRouted_1,maskRouted_0};
assign _zz_io_chosen = io_chosenOH[1];
assign io_chosen = _zz_io_chosen;
always @(posedge clk) begin
if(reset) begin
locked <= 1'b0;
maskLocked_0 <= 1'b0;
maskLocked_1 <= 1'b1;
end else begin
if(io_output_valid) begin
maskLocked_0 <= maskRouted_0;
maskLocked_1 <= maskRouted_1;
end
if(io_output_valid) begin
locked <= 1'b1;
end
if(io_output_fire) begin
locked <= 1'b0;
end
end
end
endmodule
module Axi4PeripheralStreamFifo_3_86b7e1c47b934a8a97a62bda8ee6a75d (
input wire io_push_valid,
output wire io_push_ready,
input wire [7:0] io_push_payload_data,
output wire io_pop_valid,
input wire io_pop_ready,
output wire [7:0] io_pop_payload_data,
input wire io_flush,
output wire [8:0] io_occupancy,
output wire [8:0] io_availability,
input wire clk,
input wire reset
);
reg [7:0] logic_ram_spinal_port1;
reg _zz_1;
wire logic_ptr_doPush;
wire logic_ptr_doPop;
wire logic_ptr_full;
wire logic_ptr_empty;
reg [8:0] logic_ptr_push;
reg [8:0] logic_ptr_pop;
wire [8:0] logic_ptr_occupancy;
wire [8:0] logic_ptr_popOnIo;
wire when_Stream_l1248;
reg logic_ptr_wentUp;
wire io_push_fire;
wire logic_push_onRam_write_valid;
wire [7:0] logic_push_onRam_write_payload_address;
wire [7:0] logic_push_onRam_write_payload_data_data;
wire logic_pop_addressGen_valid;
reg logic_pop_addressGen_ready;
wire [7:0] logic_pop_addressGen_payload;
wire logic_pop_addressGen_fire;
wire logic_pop_sync_readArbitation_valid;
wire logic_pop_sync_readArbitation_ready;
wire [7:0] logic_pop_sync_readArbitation_payload;
reg logic_pop_addressGen_rValid;
reg [7:0] logic_pop_addressGen_rData;
wire when_Stream_l375;
wire logic_pop_sync_readPort_cmd_valid;
wire [7:0] logic_pop_sync_readPort_cmd_payload;
wire [7:0] logic_pop_sync_readPort_rsp_data;
wire logic_pop_sync_readArbitation_translated_valid;
wire logic_pop_sync_readArbitation_translated_ready;
wire [7:0] logic_pop_sync_readArbitation_translated_payload_data;
wire logic_pop_sync_readArbitation_fire;
reg [8:0] logic_pop_sync_popReg;
reg [7:0] logic_ram [0:255];
always @(posedge clk) begin
if(_zz_1) begin
logic_ram[logic_push_onRam_write_payload_address] <= logic_push_onRam_write_payload_data_data;
end
end
always @(posedge clk) begin
if(logic_pop_sync_readPort_cmd_valid) begin
logic_ram_spinal_port1 <= logic_ram[logic_pop_sync_readPort_cmd_payload];
end
end
always @(*) begin
_zz_1 = 1'b0;
if(logic_push_onRam_write_valid) begin
_zz_1 = 1'b1;
end
end
assign when_Stream_l1248 = (logic_ptr_doPush != logic_ptr_doPop);
assign logic_ptr_full = (((logic_ptr_push ^ logic_ptr_popOnIo) ^ 9'h100) == 9'h0);
assign logic_ptr_empty = (logic_ptr_push == logic_ptr_pop);
assign logic_ptr_occupancy = (logic_ptr_push - logic_ptr_popOnIo);
assign io_push_ready = (! logic_ptr_full);
assign io_push_fire = (io_push_valid && io_push_ready);
assign logic_ptr_doPush = io_push_fire;
assign logic_push_onRam_write_valid = io_push_fire;
assign logic_push_onRam_write_payload_address = logic_ptr_push[7:0];
assign logic_push_onRam_write_payload_data_data = io_push_payload_data;
assign logic_pop_addressGen_valid = (! logic_ptr_empty);
assign logic_pop_addressGen_payload = logic_ptr_pop[7:0];
assign logic_pop_addressGen_fire = (logic_pop_addressGen_valid && logic_pop_addressGen_ready);
assign logic_ptr_doPop = logic_pop_addressGen_fire;
always @(*) begin
logic_pop_addressGen_ready = logic_pop_sync_readArbitation_ready;
if(when_Stream_l375) begin
logic_pop_addressGen_ready = 1'b1;
end
end
assign when_Stream_l375 = (! logic_pop_sync_readArbitation_valid);
assign logic_pop_sync_readArbitation_valid = logic_pop_addressGen_rValid;
assign logic_pop_sync_readArbitation_payload = logic_pop_addressGen_rData;
assign logic_pop_sync_readPort_rsp_data = logic_ram_spinal_port1[7 : 0];
assign logic_pop_sync_readPort_cmd_valid = logic_pop_addressGen_fire;
assign logic_pop_sync_readPort_cmd_payload = logic_pop_addressGen_payload;
assign logic_pop_sync_readArbitation_translated_valid = logic_pop_sync_readArbitation_valid;
assign logic_pop_sync_readArbitation_ready = logic_pop_sync_readArbitation_translated_ready;
assign logic_pop_sync_readArbitation_translated_payload_data = logic_pop_sync_readPort_rsp_data;
assign io_pop_valid = logic_pop_sync_readArbitation_translated_valid;
assign logic_pop_sync_readArbitation_translated_ready = io_pop_ready;
assign io_pop_payload_data = logic_pop_sync_readArbitation_translated_payload_data;
assign logic_pop_sync_readArbitation_fire = (logic_pop_sync_readArbitation_valid && logic_pop_sync_readArbitation_ready);
assign logic_ptr_popOnIo = logic_pop_sync_popReg;
assign io_occupancy = logic_ptr_occupancy;
assign io_availability = (9'h100 - logic_ptr_occupancy);
always @(posedge clk) begin
if(reset) begin
logic_ptr_push <= 9'h0;
logic_ptr_pop <= 9'h0;
logic_ptr_wentUp <= 1'b0;
logic_pop_addressGen_rValid <= 1'b0;
logic_pop_sync_popReg <= 9'h0;
end else begin
if(when_Stream_l1248) begin
logic_ptr_wentUp <= logic_ptr_doPush;
end
if(io_flush) begin
logic_ptr_wentUp <= 1'b0;
end
if(logic_ptr_doPush) begin
logic_ptr_push <= (logic_ptr_push + 9'h001);
end
if(logic_ptr_doPop) begin
logic_ptr_pop <= (logic_ptr_pop + 9'h001);
end
if(io_flush) begin
logic_ptr_push <= 9'h0;
logic_ptr_pop <= 9'h0;
end
if(logic_pop_addressGen_ready) begin
logic_pop_addressGen_rValid <= logic_pop_addressGen_valid;
end
if(io_flush) begin
logic_pop_addressGen_rValid <= 1'b0;
end
if(logic_pop_sync_readArbitation_fire) begin
logic_pop_sync_popReg <= logic_ptr_pop;
end
if(io_flush) begin
logic_pop_sync_popReg <= 9'h0;
end
end
end
always @(posedge clk) begin
if(logic_pop_addressGen_ready) begin
logic_pop_addressGen_rData <= logic_pop_addressGen_payload;
end
end
endmodule
module Axi4PeripheralStreamFifo_2_86b7e1c47b934a8a97a62bda8ee6a75d (
input wire io_push_valid,
output wire io_push_ready,
input wire io_push_payload_kind,
input wire io_push_payload_read,
input wire io_push_payload_write,
input wire [7:0] io_push_payload_data,
output wire io_pop_valid,
input wire io_pop_ready,
output wire io_pop_payload_kind,
output wire io_pop_payload_read,
output wire io_pop_payload_write,
output wire [7:0] io_pop_payload_data,
input wire io_flush,
output wire [8:0] io_occupancy,
output wire [8:0] io_availability,
input wire clk,
input wire reset
);
reg [10:0] logic_ram_spinal_port1;
wire [10:0] _zz_logic_ram_port;
reg _zz_1;
wire logic_ptr_doPush;
wire logic_ptr_doPop;
wire logic_ptr_full;
wire logic_ptr_empty;
reg [8:0] logic_ptr_push;
reg [8:0] logic_ptr_pop;
wire [8:0] logic_ptr_occupancy;
wire [8:0] logic_ptr_popOnIo;
wire when_Stream_l1248;
reg logic_ptr_wentUp;
wire io_push_fire;
wire logic_push_onRam_write_valid;
wire [7:0] logic_push_onRam_write_payload_address;
wire logic_push_onRam_write_payload_data_kind;
wire logic_push_onRam_write_payload_data_read;
wire logic_push_onRam_write_payload_data_write;
wire [7:0] logic_push_onRam_write_payload_data_data;
wire logic_pop_addressGen_valid;
reg logic_pop_addressGen_ready;
wire [7:0] logic_pop_addressGen_payload;
wire logic_pop_addressGen_fire;
wire logic_pop_sync_readArbitation_valid;
wire logic_pop_sync_readArbitation_ready;
wire [7:0] logic_pop_sync_readArbitation_payload;
reg logic_pop_addressGen_rValid;
reg [7:0] logic_pop_addressGen_rData;
wire when_Stream_l375;
wire logic_pop_sync_readPort_cmd_valid;
wire [7:0] logic_pop_sync_readPort_cmd_payload;
wire logic_pop_sync_readPort_rsp_kind;
wire logic_pop_sync_readPort_rsp_read;
wire logic_pop_sync_readPort_rsp_write;
wire [7:0] logic_pop_sync_readPort_rsp_data;
wire [10:0] _zz_logic_pop_sync_readPort_rsp_kind;
wire logic_pop_sync_readArbitation_translated_valid;
wire logic_pop_sync_readArbitation_translated_ready;
wire logic_pop_sync_readArbitation_translated_payload_kind;
wire logic_pop_sync_readArbitation_translated_payload_read;
wire logic_pop_sync_readArbitation_translated_payload_write;
wire [7:0] logic_pop_sync_readArbitation_translated_payload_data;
wire logic_pop_sync_readArbitation_fire;
reg [8:0] logic_pop_sync_popReg;
reg [10:0] logic_ram [0:255];
assign _zz_logic_ram_port = {logic_push_onRam_write_payload_data_data,{logic_push_onRam_write_payload_data_write,{logic_push_onRam_write_payload_data_read,logic_push_onRam_write_payload_data_kind}}};
always @(posedge clk) begin
if(_zz_1) begin
logic_ram[logic_push_onRam_write_payload_address] <= _zz_logic_ram_port;
end
end
always @(posedge clk) begin
if(logic_pop_sync_readPort_cmd_valid) begin
logic_ram_spinal_port1 <= logic_ram[logic_pop_sync_readPort_cmd_payload];
end
end
always @(*) begin
_zz_1 = 1'b0;
if(logic_push_onRam_write_valid) begin
_zz_1 = 1'b1;
end
end
assign when_Stream_l1248 = (logic_ptr_doPush != logic_ptr_doPop);
assign logic_ptr_full = (((logic_ptr_push ^ logic_ptr_popOnIo) ^ 9'h100) == 9'h0);
assign logic_ptr_empty = (logic_ptr_push == logic_ptr_pop);
assign logic_ptr_occupancy = (logic_ptr_push - logic_ptr_popOnIo);
assign io_push_ready = (! logic_ptr_full);
assign io_push_fire = (io_push_valid && io_push_ready);
assign logic_ptr_doPush = io_push_fire;
assign logic_push_onRam_write_valid = io_push_fire;
assign logic_push_onRam_write_payload_address = logic_ptr_push[7:0];
assign logic_push_onRam_write_payload_data_kind = io_push_payload_kind;
assign logic_push_onRam_write_payload_data_read = io_push_payload_read;
assign logic_push_onRam_write_payload_data_write = io_push_payload_write;
assign logic_push_onRam_write_payload_data_data = io_push_payload_data;
assign logic_pop_addressGen_valid = (! logic_ptr_empty);
assign logic_pop_addressGen_payload = logic_ptr_pop[7:0];
assign logic_pop_addressGen_fire = (logic_pop_addressGen_valid && logic_pop_addressGen_ready);
assign logic_ptr_doPop = logic_pop_addressGen_fire;
always @(*) begin
logic_pop_addressGen_ready = logic_pop_sync_readArbitation_ready;
if(when_Stream_l375) begin
logic_pop_addressGen_ready = 1'b1;
end
end
assign when_Stream_l375 = (! logic_pop_sync_readArbitation_valid);
assign logic_pop_sync_readArbitation_valid = logic_pop_addressGen_rValid;
assign logic_pop_sync_readArbitation_payload = logic_pop_addressGen_rData;
assign _zz_logic_pop_sync_readPort_rsp_kind = logic_ram_spinal_port1;
assign logic_pop_sync_readPort_rsp_kind = _zz_logic_pop_sync_readPort_rsp_kind[0];
assign logic_pop_sync_readPort_rsp_read = _zz_logic_pop_sync_readPort_rsp_kind[1];
assign logic_pop_sync_readPort_rsp_write = _zz_logic_pop_sync_readPort_rsp_kind[2];
assign logic_pop_sync_readPort_rsp_data = _zz_logic_pop_sync_readPort_rsp_kind[10 : 3];
assign logic_pop_sync_readPort_cmd_valid = logic_pop_addressGen_fire;
assign logic_pop_sync_readPort_cmd_payload = logic_pop_addressGen_payload;
assign logic_pop_sync_readArbitation_translated_valid = logic_pop_sync_readArbitation_valid;
assign logic_pop_sync_readArbitation_ready = logic_pop_sync_readArbitation_translated_ready;
assign logic_pop_sync_readArbitation_translated_payload_kind = logic_pop_sync_readPort_rsp_kind;
assign logic_pop_sync_readArbitation_translated_payload_read = logic_pop_sync_readPort_rsp_read;
assign logic_pop_sync_readArbitation_translated_payload_write = logic_pop_sync_readPort_rsp_write;
assign logic_pop_sync_readArbitation_translated_payload_data = logic_pop_sync_readPort_rsp_data;
assign io_pop_valid = logic_pop_sync_readArbitation_translated_valid;
assign logic_pop_sync_readArbitation_translated_ready = io_pop_ready;
assign io_pop_payload_kind = logic_pop_sync_readArbitation_translated_payload_kind;
assign io_pop_payload_read = logic_pop_sync_readArbitation_translated_payload_read;
assign io_pop_payload_write = logic_pop_sync_readArbitation_translated_payload_write;
assign io_pop_payload_data = logic_pop_sync_readArbitation_translated_payload_data;
assign logic_pop_sync_readArbitation_fire = (logic_pop_sync_readArbitation_valid && logic_pop_sync_readArbitation_ready);
assign logic_ptr_popOnIo = logic_pop_sync_popReg;
assign io_occupancy = logic_ptr_occupancy;
assign io_availability = (9'h100 - logic_ptr_occupancy);
always @(posedge clk) begin
if(reset) begin
logic_ptr_push <= 9'h0;
logic_ptr_pop <= 9'h0;
logic_ptr_wentUp <= 1'b0;
logic_pop_addressGen_rValid <= 1'b0;
logic_pop_sync_popReg <= 9'h0;
end else begin
if(when_Stream_l1248) begin
logic_ptr_wentUp <= logic_ptr_doPush;
end
if(io_flush) begin
logic_ptr_wentUp <= 1'b0;
end
if(logic_ptr_doPush) begin
logic_ptr_push <= (logic_ptr_push + 9'h001);
end
if(logic_ptr_doPop) begin
logic_ptr_pop <= (logic_ptr_pop + 9'h001);
end
if(io_flush) begin
logic_ptr_push <= 9'h0;
logic_ptr_pop <= 9'h0;
end
if(logic_pop_addressGen_ready) begin
logic_pop_addressGen_rValid <= logic_pop_addressGen_valid;
end
if(io_flush) begin
logic_pop_addressGen_rValid <= 1'b0;
end
if(logic_pop_sync_readArbitation_fire) begin
logic_pop_sync_popReg <= logic_ptr_pop;
end
if(io_flush) begin
logic_pop_sync_popReg <= 9'h0;
end
end
end
always @(posedge clk) begin
if(logic_pop_addressGen_ready) begin
logic_pop_addressGen_rData <= logic_pop_addressGen_payload;
end
end
endmodule
module Axi4PeripheralTopLevel_86b7e1c47b934a8a97a62bda8ee6a75d (
input wire io_config_kind_cpol,
input wire io_config_kind_cpha,
input wire [11:0] io_config_sclkToggle,
input wire [1:0] io_config_mod,
input wire [3:0] io_config_ss_activeHigh,
input wire [11:0] io_config_ss_setup,
input wire [11:0] io_config_ss_hold,
input wire [11:0] io_config_ss_disable,
input wire io_cmd_valid,
output reg io_cmd_ready,
input wire io_cmd_payload_kind,
input wire io_cmd_payload_read,
input wire io_cmd_payload_write,
input wire [7:0] io_cmd_payload_data,
output wire io_rsp_valid,
output wire [7:0] io_rsp_payload_data,
output wire [0:0] io_spi_sclk_write,
output reg io_spi_data_0_writeEnable,
input wire [0:0] io_spi_data_0_read,
output reg [0:0] io_spi_data_0_write,
output reg io_spi_data_1_writeEnable,
input wire [0:0] io_spi_data_1_read,
output reg [0:0] io_spi_data_1_write,
output reg io_spi_data_2_writeEnable,
input wire [0:0] io_spi_data_2_read,
output reg [0:0] io_spi_data_2_write,
output reg io_spi_data_3_writeEnable,
input wire [0:0] io_spi_data_3_read,
output reg [0:0] io_spi_data_3_write,
output wire [3:0] io_spi_ss,
input wire clk,
input wire reset
);
reg [0:0] _zz_outputPhy_dataWrite_3;
wire [2:0] _zz_outputPhy_dataWrite_4;
reg [1:0] _zz_outputPhy_dataWrite_5;
wire [1:0] _zz_outputPhy_dataWrite_6;
wire [2:0] _zz_outputPhy_dataWrite_7;
reg [3:0] _zz_outputPhy_dataWrite_8;
wire [0:0] _zz_outputPhy_dataWrite_9;
wire [2:0] _zz_outputPhy_dataWrite_10;
wire [3:0] _zz_inputPhy_dataRead;
wire [3:0] _zz_inputPhy_dataRead_1;
wire [3:0] _zz_inputPhy_dataRead_2;
wire [3:0] _zz_inputPhy_dataRead_3;
wire [3:0] _zz_inputPhy_dataRead_4;
wire [3:0] _zz_inputPhy_dataRead_5;
wire [3:0] _zz_inputPhy_dataRead_6;
wire [8:0] _zz_inputPhy_bufferNext;
wire [10:0] _zz_inputPhy_bufferNext_1;
reg [11:0] timer_counter;
reg timer_reset;
wire timer_ss_setupHit;
wire timer_ss_holdHit;
wire timer_ss_disableHit;
wire timer_sclkToggleHit;
reg fsm_state;
reg [2:0] fsm_counter;
reg [2:0] _zz_fsm_counterPlus;
wire [2:0] fsm_counterPlus;
reg fsm_fastRate;
reg fsm_isDdr;
reg [2:0] fsm_counterMax;
reg fsm_lateSampling;
reg fsm_readFill;
reg fsm_readDone;
reg [3:0] fsm_ss;
wire when_SpiXdrMasterCtrl_l741;
wire when_SpiXdrMasterCtrl_l744;
wire when_SpiXdrMasterCtrl_l751;
wire when_SpiXdrMasterCtrl_l753;
wire when_SpiXdrMasterCtrl_l760;
wire when_SpiXdrMasterCtrl_l766;
wire when_SpiXdrMasterCtrl_l783;
reg [0:0] outputPhy_sclkWrite;
wire [0:0] _zz_io_spi_sclk_write;
wire when_SpiXdrMasterCtrl_l798;
reg [3:0] outputPhy_dataWrite;
reg [2:0] outputPhy_widthSel;
reg [2:0] outputPhy_offset;
wire [7:0] _zz_outputPhy_dataWrite;
wire [7:0] _zz_outputPhy_dataWrite_1;
wire [7:0] _zz_outputPhy_dataWrite_2;
wire when_SpiXdrMasterCtrl_l841;
wire when_SpiXdrMasterCtrl_l841_1;
reg [1:0] io_config_mod_delay_1;
reg [1:0] inputPhy_mod;
reg fsm_readFill_delay_1;
reg inputPhy_readFill;
reg fsm_readDone_delay_1;
reg inputPhy_readDone;
reg [6:0] inputPhy_buffer;
reg [7:0] inputPhy_bufferNext;
reg [2:0] inputPhy_widthSel;
wire [3:0] inputPhy_dataWrite;
reg [3:0] inputPhy_dataRead;
reg fsm_state_delay_1;
reg fsm_state_delay_2;
wire when_SpiXdrMasterCtrl_l863;
reg [3:0] inputPhy_dataReadBuffer;
assign _zz_outputPhy_dataWrite_4 = (outputPhy_offset - fsm_counter);
assign _zz_outputPhy_dataWrite_6 = (_zz_outputPhy_dataWrite_7 >>> 1'd1);
assign _zz_outputPhy_dataWrite_7 = (outputPhy_offset - fsm_counter);
assign _zz_outputPhy_dataWrite_9 = (_zz_outputPhy_dataWrite_10 >>> 2'd2);
assign _zz_outputPhy_dataWrite_10 = (outputPhy_offset - fsm_counter);
assign _zz_inputPhy_dataRead = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}};
assign _zz_inputPhy_dataRead_1 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}};
assign _zz_inputPhy_dataRead_2 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}};
assign _zz_inputPhy_dataRead_3 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}};
assign _zz_inputPhy_dataRead_4 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}};
assign _zz_inputPhy_dataRead_5 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}};
assign _zz_inputPhy_dataRead_6 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}};
assign _zz_inputPhy_bufferNext = {inputPhy_buffer,inputPhy_dataRead[1 : 0]};
assign _zz_inputPhy_bufferNext_1 = {inputPhy_buffer,inputPhy_dataRead[3 : 0]};
always @(*) begin
case(_zz_outputPhy_dataWrite_4)
3'b000 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[0 : 0];
3'b001 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[1 : 1];
3'b010 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[2 : 2];
3'b011 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[3 : 3];
3'b100 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[4 : 4];
3'b101 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[5 : 5];
3'b110 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[6 : 6];
default : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[7 : 7];
endcase
end
always @(*) begin
case(_zz_outputPhy_dataWrite_6)
2'b00 : _zz_outputPhy_dataWrite_5 = _zz_outputPhy_dataWrite_1[1 : 0];
2'b01 : _zz_outputPhy_dataWrite_5 = _zz_outputPhy_dataWrite_1[3 : 2];
2'b10 : _zz_outputPhy_dataWrite_5 = _zz_outputPhy_dataWrite_1[5 : 4];
default : _zz_outputPhy_dataWrite_5 = _zz_outputPhy_dataWrite_1[7 : 6];
endcase
end
always @(*) begin
case(_zz_outputPhy_dataWrite_9)
1'b0 : _zz_outputPhy_dataWrite_8 = _zz_outputPhy_dataWrite_2[3 : 0];
default : _zz_outputPhy_dataWrite_8 = _zz_outputPhy_dataWrite_2[7 : 4];
endcase
end
always @(*) begin
timer_reset = 1'b0;
if(io_cmd_valid) begin
if(when_SpiXdrMasterCtrl_l741) begin
timer_reset = timer_sclkToggleHit;
end else begin
if(!when_SpiXdrMasterCtrl_l760) begin
if(when_SpiXdrMasterCtrl_l766) begin
if(timer_ss_holdHit) begin
timer_reset = 1'b1;
end
end
end
end
end
if(when_SpiXdrMasterCtrl_l783) begin
timer_reset = 1'b1;
end
end
assign timer_ss_setupHit = (timer_counter == io_config_ss_setup);
assign timer_ss_holdHit = (timer_counter == io_config_ss_hold);
assign timer_ss_disableHit = (timer_counter == io_config_ss_disable);
assign timer_sclkToggleHit = (timer_counter == io_config_sclkToggle);
always @(*) begin
_zz_fsm_counterPlus = 3'bxxx;
case(io_config_mod)
2'b00 : begin
_zz_fsm_counterPlus = 3'b001;
end
2'b01 : begin
_zz_fsm_counterPlus = 3'b010;
end
2'b10 : begin
_zz_fsm_counterPlus = 3'b100;
end
default : begin
end
endcase
end
assign fsm_counterPlus = (fsm_counter + _zz_fsm_counterPlus);
always @(*) begin
fsm_fastRate = 1'bx;
case(io_config_mod)
2'b00 : begin
fsm_fastRate = 1'b0;
end
2'b01 : begin
fsm_fastRate = 1'b0;
end
2'b10 : begin
fsm_fastRate = 1'b0;
end
default : begin
end
endcase
end
always @(*) begin
fsm_isDdr = 1'bx;
case(io_config_mod)
2'b00 : begin
fsm_isDdr = 1'b0;
end
2'b01 : begin
fsm_isDdr = 1'b0;
end
2'b10 : begin
fsm_isDdr = 1'b0;
end
default : begin
end
endcase
end
always @(*) begin
fsm_counterMax = 3'bxxx;
case(io_config_mod)
2'b00 : begin
fsm_counterMax = 3'b111;
end
2'b01 : begin
fsm_counterMax = 3'b110;
end
2'b10 : begin
fsm_counterMax = 3'b100;
end
default : begin
end
endcase
end
always @(*) begin
fsm_lateSampling = 1'bx;
case(io_config_mod)
2'b00 : begin
fsm_lateSampling = 1'b1;
end
2'b01 : begin
fsm_lateSampling = 1'b1;
end
2'b10 : begin
fsm_lateSampling = 1'b1;
end
default : begin
end
endcase
end
always @(*) begin
fsm_readFill = 1'b0;
if(io_cmd_valid) begin
if(when_SpiXdrMasterCtrl_l741) begin
if(when_SpiXdrMasterCtrl_l744) begin
fsm_readFill = 1'b1;
end
end
end
end
always @(*) begin
fsm_readDone = 1'b0;
if(io_cmd_valid) begin
if(when_SpiXdrMasterCtrl_l741) begin
if(when_SpiXdrMasterCtrl_l744) begin
fsm_readDone = (io_cmd_payload_read && (fsm_counter == fsm_counterMax));
end
end
end
end
assign io_spi_ss = (~ (fsm_ss ^ io_config_ss_activeHigh));
always @(*) begin
io_cmd_ready = 1'b0;
if(io_cmd_valid) begin
if(when_SpiXdrMasterCtrl_l741) begin
if(when_SpiXdrMasterCtrl_l751) begin
if(when_SpiXdrMasterCtrl_l753) begin
io_cmd_ready = 1'b1;
end
end
end else begin
if(when_SpiXdrMasterCtrl_l760) begin
if(timer_ss_setupHit) begin
io_cmd_ready = 1'b1;
end
end else begin
if(!when_SpiXdrMasterCtrl_l766) begin
if(timer_ss_disableHit) begin
io_cmd_ready = 1'b1;
end
end
end
end
end
end
assign when_SpiXdrMasterCtrl_l741 = (! io_cmd_payload_kind);
assign when_SpiXdrMasterCtrl_l744 = ((timer_sclkToggleHit && (((! fsm_state) ^ fsm_lateSampling) || fsm_isDdr)) || fsm_fastRate);
assign when_SpiXdrMasterCtrl_l751 = ((timer_sclkToggleHit && (fsm_state || fsm_isDdr)) || fsm_fastRate);
assign when_SpiXdrMasterCtrl_l753 = (fsm_counter == fsm_counterMax);
assign when_SpiXdrMasterCtrl_l760 = io_cmd_payload_data[7];
assign when_SpiXdrMasterCtrl_l766 = (! fsm_state);
assign when_SpiXdrMasterCtrl_l783 = ((! io_cmd_valid) || io_cmd_ready);
always @(*) begin
outputPhy_sclkWrite = 1'b0;
if(when_SpiXdrMasterCtrl_l798) begin
case(io_config_mod)
2'b00 : begin
outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0);
end
2'b01 : begin
outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0);
end
2'b10 : begin
outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0);
end
default : begin
end
endcase
end
end
assign _zz_io_spi_sclk_write[0] = io_config_kind_cpol;
assign io_spi_sclk_write = (outputPhy_sclkWrite ^ _zz_io_spi_sclk_write);
assign when_SpiXdrMasterCtrl_l798 = (io_cmd_valid && (! io_cmd_payload_kind));
always @(*) begin
outputPhy_widthSel = 3'bxxx;
case(io_config_mod)
2'b00 : begin
outputPhy_widthSel = 3'b000;
end
2'b01 : begin
outputPhy_widthSel = 3'b001;
end
2'b10 : begin
outputPhy_widthSel = 3'b010;
end
default : begin
end
endcase
end
always @(*) begin
outputPhy_offset = 3'bxxx;
case(io_config_mod)
2'b00 : begin
outputPhy_offset = 3'b111;
end
2'b01 : begin
outputPhy_offset = 3'b111;
end
2'b10 : begin
outputPhy_offset = 3'b111;
end
default : begin
end
endcase
end
always @(*) begin
outputPhy_dataWrite = 4'bxxxx;
case(outputPhy_widthSel)
3'b000 : begin
outputPhy_dataWrite[0 : 0] = _zz_outputPhy_dataWrite_3;
end
3'b001 : begin
outputPhy_dataWrite[1 : 0] = _zz_outputPhy_dataWrite_5;
end
3'b010 : begin
outputPhy_dataWrite[3 : 0] = _zz_outputPhy_dataWrite_8;
end
default : begin
end
endcase
end
assign _zz_outputPhy_dataWrite = io_cmd_payload_data;
assign _zz_outputPhy_dataWrite_1 = io_cmd_payload_data;
assign _zz_outputPhy_dataWrite_2 = io_cmd_payload_data;
always @(*) begin
io_spi_data_0_writeEnable = 1'b0;
case(io_config_mod)
2'b00 : begin
io_spi_data_0_writeEnable = 1'b1;
end
2'b01 : begin
if(when_SpiXdrMasterCtrl_l841) begin
io_spi_data_0_writeEnable = 1'b1;
end
end
2'b10 : begin
if(when_SpiXdrMasterCtrl_l841_1) begin
io_spi_data_0_writeEnable = 1'b1;
end
end
default : begin
end
endcase
end
always @(*) begin
io_spi_data_1_writeEnable = 1'b0;
case(io_config_mod)
2'b01 : begin
if(when_SpiXdrMasterCtrl_l841) begin
io_spi_data_1_writeEnable = 1'b1;
end
end
2'b10 : begin
if(when_SpiXdrMasterCtrl_l841_1) begin
io_spi_data_1_writeEnable = 1'b1;
end
end
default : begin
end
endcase
end
always @(*) begin
io_spi_data_2_writeEnable = 1'b0;
case(io_config_mod)
2'b10 : begin
if(when_SpiXdrMasterCtrl_l841_1) begin
io_spi_data_2_writeEnable = 1'b1;
end
end
default : begin
end
endcase
end
always @(*) begin
io_spi_data_3_writeEnable = 1'b0;
case(io_config_mod)
2'b10 : begin
if(when_SpiXdrMasterCtrl_l841_1) begin
io_spi_data_3_writeEnable = 1'b1;
end
end
default : begin
end
endcase
end
always @(*) begin
io_spi_data_0_write = 1'bx;
case(io_config_mod)
2'b00 : begin
io_spi_data_0_write[0] = (outputPhy_dataWrite[0] || (! (io_cmd_valid && io_cmd_payload_write)));
end
2'b01 : begin
io_spi_data_0_write[0] = outputPhy_dataWrite[0];
end
2'b10 : begin
io_spi_data_0_write[0] = outputPhy_dataWrite[0];
end
default : begin
end
endcase
end
always @(*) begin
io_spi_data_1_write = 1'bx;
case(io_config_mod)
2'b01 : begin
io_spi_data_1_write[0] = outputPhy_dataWrite[1];
end
2'b10 : begin
io_spi_data_1_write[0] = outputPhy_dataWrite[1];
end
default : begin
end
endcase
end
always @(*) begin
io_spi_data_2_write = 1'bx;
case(io_config_mod)
2'b10 : begin
io_spi_data_2_write[0] = outputPhy_dataWrite[2];
end
default : begin
end
endcase
end
always @(*) begin
io_spi_data_3_write = 1'bx;
case(io_config_mod)
2'b10 : begin
io_spi_data_3_write[0] = outputPhy_dataWrite[3];
end
default : begin
end
endcase
end
assign when_SpiXdrMasterCtrl_l841 = (io_cmd_valid && io_cmd_payload_write);
assign when_SpiXdrMasterCtrl_l841_1 = (io_cmd_valid && io_cmd_payload_write);
always @(*) begin
inputPhy_bufferNext = 8'bxxxxxxxx;
case(inputPhy_widthSel)
3'b000 : begin
inputPhy_bufferNext = {inputPhy_buffer,inputPhy_dataRead[0 : 0]};
end
3'b001 : begin
inputPhy_bufferNext = _zz_inputPhy_bufferNext[7:0];
end
3'b010 : begin
inputPhy_bufferNext = _zz_inputPhy_bufferNext_1[7:0];
end
default : begin
end
endcase
end
always @(*) begin
inputPhy_widthSel = 3'bxxx;
case(inputPhy_mod)
2'b00 : begin
inputPhy_widthSel = 3'b000;
end
2'b01 : begin
inputPhy_widthSel = 3'b001;
end
2'b10 : begin
inputPhy_widthSel = 3'b010;
end
default : begin
end
endcase
end
assign when_SpiXdrMasterCtrl_l863 = (! fsm_state_delay_2);
always @(*) begin
inputPhy_dataRead = 4'bxxxx;
case(inputPhy_mod)
2'b00 : begin
inputPhy_dataRead[0] = _zz_inputPhy_dataRead[1];
end
2'b01 : begin
inputPhy_dataRead[0] = _zz_inputPhy_dataRead_1[0];
inputPhy_dataRead[1] = _zz_inputPhy_dataRead_2[1];
end
2'b10 : begin
inputPhy_dataRead[0] = _zz_inputPhy_dataRead_3[0];
inputPhy_dataRead[1] = _zz_inputPhy_dataRead_4[1];
inputPhy_dataRead[2] = _zz_inputPhy_dataRead_5[2];
inputPhy_dataRead[3] = _zz_inputPhy_dataRead_6[3];
end
default : begin
end
endcase
end
assign io_rsp_valid = inputPhy_readDone;
assign io_rsp_payload_data = inputPhy_bufferNext;
always @(posedge clk) begin
timer_counter <= (timer_counter + 12'h001);
if(timer_reset) begin
timer_counter <= 12'h0;
end
io_config_mod_delay_1 <= io_config_mod;
inputPhy_mod <= io_config_mod_delay_1;
fsm_state_delay_1 <= fsm_state;
fsm_state_delay_2 <= fsm_state_delay_1;
if(when_SpiXdrMasterCtrl_l863) begin
inputPhy_dataReadBuffer <= {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}};
end
case(inputPhy_widthSel)
3'b000 : begin
if(inputPhy_readFill) begin
inputPhy_buffer <= inputPhy_bufferNext[6:0];
end
end
3'b001 : begin
if(inputPhy_readFill) begin
inputPhy_buffer <= inputPhy_bufferNext[6:0];
end
end
3'b010 : begin
if(inputPhy_readFill) begin
inputPhy_buffer <= inputPhy_bufferNext[6:0];
end
end
default : begin
end
endcase
end
always @(posedge clk) begin
if(reset) begin
fsm_state <= 1'b0;
fsm_counter <= 3'b000;
fsm_ss <= 4'b0000;
fsm_readFill_delay_1 <= 1'b0;
inputPhy_readFill <= 1'b0;
fsm_readDone_delay_1 <= 1'b0;
inputPhy_readDone <= 1'b0;
end else begin
if(io_cmd_valid) begin
if(when_SpiXdrMasterCtrl_l741) begin
if(timer_sclkToggleHit) begin
fsm_state <= (! fsm_state);
end
if(when_SpiXdrMasterCtrl_l751) begin
fsm_counter <= fsm_counterPlus;
if(when_SpiXdrMasterCtrl_l753) begin
fsm_state <= 1'b0;
end
end
end else begin
if(when_SpiXdrMasterCtrl_l760) begin
fsm_ss[io_cmd_payload_data[1 : 0]] <= 1'b1;
end else begin
if(when_SpiXdrMasterCtrl_l766) begin
if(timer_ss_holdHit) begin
fsm_state <= 1'b1;
end
end else begin
fsm_ss[io_cmd_payload_data[1 : 0]] <= 1'b0;
end
end
end
end
if(when_SpiXdrMasterCtrl_l783) begin
fsm_state <= 1'b0;
fsm_counter <= 3'b000;
end
fsm_readFill_delay_1 <= fsm_readFill;
inputPhy_readFill <= fsm_readFill_delay_1;
fsm_readDone_delay_1 <= fsm_readDone;
inputPhy_readDone <= fsm_readDone_delay_1;
end
end
endmodule
//Axi4PeripheralStreamFifo_1 replaced by Axi4PeripheralStreamFifo_86b7e1c47b934a8a97a62bda8ee6a75d
module Axi4PeripheralStreamFifo_86b7e1c47b934a8a97a62bda8ee6a75d (
input wire io_push_valid,
output wire io_push_ready,
input wire [7:0] io_push_payload,
output wire io_pop_valid,
input wire io_pop_ready,
output wire [7:0] io_pop_payload,
input wire io_flush,
output wire [7:0] io_occupancy,
output wire [7:0] io_availability,
input wire clk,
input wire reset
);
reg [7:0] logic_ram_spinal_port1;
reg _zz_1;
wire logic_ptr_doPush;
wire logic_ptr_doPop;
wire logic_ptr_full;
wire logic_ptr_empty;
reg [7:0] logic_ptr_push;
reg [7:0] logic_ptr_pop;
wire [7:0] logic_ptr_occupancy;
wire [7:0] logic_ptr_popOnIo;
wire when_Stream_l1248;
reg logic_ptr_wentUp;
wire io_push_fire;
wire logic_push_onRam_write_valid;
wire [6:0] logic_push_onRam_write_payload_address;
wire [7:0] logic_push_onRam_write_payload_data;
wire logic_pop_addressGen_valid;
reg logic_pop_addressGen_ready;
wire [6:0] logic_pop_addressGen_payload;
wire logic_pop_addressGen_fire;
wire logic_pop_sync_readArbitation_valid;
wire logic_pop_sync_readArbitation_ready;
wire [6:0] logic_pop_sync_readArbitation_payload;
reg logic_pop_addressGen_rValid;
reg [6:0] logic_pop_addressGen_rData;
wire when_Stream_l375;
wire logic_pop_sync_readPort_cmd_valid;
wire [6:0] logic_pop_sync_readPort_cmd_payload;
wire [7:0] logic_pop_sync_readPort_rsp;
wire logic_pop_sync_readArbitation_translated_valid;
wire logic_pop_sync_readArbitation_translated_ready;
wire [7:0] logic_pop_sync_readArbitation_translated_payload;
wire logic_pop_sync_readArbitation_fire;
reg [7:0] logic_pop_sync_popReg;
reg [7:0] logic_ram [0:127];
always @(posedge clk) begin
if(_zz_1) begin
logic_ram[logic_push_onRam_write_payload_address] <= logic_push_onRam_write_payload_data;
end
end
always @(posedge clk) begin
if(logic_pop_sync_readPort_cmd_valid) begin
logic_ram_spinal_port1 <= logic_ram[logic_pop_sync_readPort_cmd_payload];
end
end
always @(*) begin
_zz_1 = 1'b0;
if(logic_push_onRam_write_valid) begin
_zz_1 = 1'b1;
end
end
assign when_Stream_l1248 = (logic_ptr_doPush != logic_ptr_doPop);
assign logic_ptr_full = (((logic_ptr_push ^ logic_ptr_popOnIo) ^ 8'h80) == 8'h0);
assign logic_ptr_empty = (logic_ptr_push == logic_ptr_pop);
assign logic_ptr_occupancy = (logic_ptr_push - logic_ptr_popOnIo);
assign io_push_ready = (! logic_ptr_full);
assign io_push_fire = (io_push_valid && io_push_ready);
assign logic_ptr_doPush = io_push_fire;
assign logic_push_onRam_write_valid = io_push_fire;
assign logic_push_onRam_write_payload_address = logic_ptr_push[6:0];
assign logic_push_onRam_write_payload_data = io_push_payload;
assign logic_pop_addressGen_valid = (! logic_ptr_empty);
assign logic_pop_addressGen_payload = logic_ptr_pop[6:0];
assign logic_pop_addressGen_fire = (logic_pop_addressGen_valid && logic_pop_addressGen_ready);
assign logic_ptr_doPop = logic_pop_addressGen_fire;
always @(*) begin
logic_pop_addressGen_ready = logic_pop_sync_readArbitation_ready;
if(when_Stream_l375) begin
logic_pop_addressGen_ready = 1'b1;
end
end
assign when_Stream_l375 = (! logic_pop_sync_readArbitation_valid);
assign logic_pop_sync_readArbitation_valid = logic_pop_addressGen_rValid;
assign logic_pop_sync_readArbitation_payload = logic_pop_addressGen_rData;
assign logic_pop_sync_readPort_rsp = logic_ram_spinal_port1;
assign logic_pop_sync_readPort_cmd_valid = logic_pop_addressGen_fire;
assign logic_pop_sync_readPort_cmd_payload = logic_pop_addressGen_payload;
assign logic_pop_sync_readArbitation_translated_valid = logic_pop_sync_readArbitation_valid;
assign logic_pop_sync_readArbitation_ready = logic_pop_sync_readArbitation_translated_ready;
assign logic_pop_sync_readArbitation_translated_payload = logic_pop_sync_readPort_rsp;
assign io_pop_valid = logic_pop_sync_readArbitation_translated_valid;
assign logic_pop_sync_readArbitation_translated_ready = io_pop_ready;
assign io_pop_payload = logic_pop_sync_readArbitation_translated_payload;
assign logic_pop_sync_readArbitation_fire = (logic_pop_sync_readArbitation_valid && logic_pop_sync_readArbitation_ready);
assign logic_ptr_popOnIo = logic_pop_sync_popReg;
assign io_occupancy = logic_ptr_occupancy;
assign io_availability = (8'h80 - logic_ptr_occupancy);
always @(posedge clk) begin
if(reset) begin
logic_ptr_push <= 8'h0;
logic_ptr_pop <= 8'h0;
logic_ptr_wentUp <= 1'b0;
logic_pop_addressGen_rValid <= 1'b0;
logic_pop_sync_popReg <= 8'h0;
end else begin
if(when_Stream_l1248) begin
logic_ptr_wentUp <= logic_ptr_doPush;
end
if(io_flush) begin
logic_ptr_wentUp <= 1'b0;
end
if(logic_ptr_doPush) begin
logic_ptr_push <= (logic_ptr_push + 8'h01);
end
if(logic_ptr_doPop) begin
logic_ptr_pop <= (logic_ptr_pop + 8'h01);
end
if(io_flush) begin
logic_ptr_push <= 8'h0;
logic_ptr_pop <= 8'h0;
end
if(logic_pop_addressGen_ready) begin
logic_pop_addressGen_rValid <= logic_pop_addressGen_valid;
end
if(io_flush) begin
logic_pop_addressGen_rValid <= 1'b0;
end
if(logic_pop_sync_readArbitation_fire) begin
logic_pop_sync_popReg <= logic_ptr_pop;
end
if(io_flush) begin
logic_pop_sync_popReg <= 8'h0;
end
end
end
always @(posedge clk) begin
if(logic_pop_addressGen_ready) begin
logic_pop_addressGen_rData <= logic_pop_addressGen_payload;
end
end
endmodule
module Axi4PeripheralUartCtrl_86b7e1c47b934a8a97a62bda8ee6a75d (
input wire [2:0] io_config_frame_dataLength,
input wire [0:0] io_config_frame_stop,
input wire [1:0] io_config_frame_parity,
input wire [19:0] io_config_clockDivider,
input wire io_write_valid,
output reg io_write_ready,
input wire [7:0] io_write_payload,
output wire io_read_valid,
input wire io_read_ready,
output wire [7:0] io_read_payload,
output wire io_uart_txd,
input wire io_uart_rxd,
output wire io_readError,
input wire io_writeBreak,
output wire io_readBreak,
input wire clk,
input wire reset
);
localparam Axi4PeripheralUartStopType_ONE = 1'd0;
localparam Axi4PeripheralUartStopType_TWO = 1'd1;
localparam Axi4PeripheralUartParityType_NONE = 2'd0;
localparam Axi4PeripheralUartParityType_EVEN = 2'd1;
localparam Axi4PeripheralUartParityType_ODD = 2'd2;
wire tx_io_write_ready;
wire tx_io_txd;
wire rx_io_read_valid;
wire [7:0] rx_io_read_payload;
wire rx_io_rts;
wire rx_io_error;
wire rx_io_break;
reg [19:0] clockDivider_counter;
wire clockDivider_tick;
reg clockDivider_tickReg;
reg io_write_thrown_valid;
wire io_write_thrown_ready;
wire [7:0] io_write_thrown_payload;
`ifndef SYNTHESIS
reg [23:0] io_config_frame_stop_string;
reg [31:0] io_config_frame_parity_string;
`endif
Axi4PeripheralUartCtrlTx_86b7e1c47b934a8a97a62bda8ee6a75d tx (
.io_configFrame_dataLength (io_config_frame_dataLength[2:0]), //i
.io_configFrame_stop (io_config_frame_stop ), //i
.io_configFrame_parity (io_config_frame_parity[1:0] ), //i
.io_samplingTick (clockDivider_tickReg ), //i
.io_write_valid (io_write_thrown_valid ), //i
.io_write_ready (tx_io_write_ready ), //o
.io_write_payload (io_write_thrown_payload[7:0] ), //i
.io_cts (1'b0 ), //i
.io_txd (tx_io_txd ), //o
.io_break (io_writeBreak ), //i
.clk (clk ), //i
.reset (reset ) //i
);
Axi4PeripheralUartCtrlRx_86b7e1c47b934a8a97a62bda8ee6a75d rx (
.io_configFrame_dataLength (io_config_frame_dataLength[2:0]), //i
.io_configFrame_stop (io_config_frame_stop ), //i
.io_configFrame_parity (io_config_frame_parity[1:0] ), //i
.io_samplingTick (clockDivider_tickReg ), //i
.io_read_valid (rx_io_read_valid ), //o
.io_read_ready (io_read_ready ), //i
.io_read_payload (rx_io_read_payload[7:0] ), //o
.io_rxd (io_uart_rxd ), //i
.io_rts (rx_io_rts ), //o
.io_error (rx_io_error ), //o
.io_break (rx_io_break ), //o
.clk (clk ), //i
.reset (reset ) //i
);
`ifndef SYNTHESIS
always @(*) begin
case(io_config_frame_stop)
Axi4PeripheralUartStopType_ONE : io_config_frame_stop_string = "ONE";
Axi4PeripheralUartStopType_TWO : io_config_frame_stop_string = "TWO";
default : io_config_frame_stop_string = "???";
endcase
end
always @(*) begin
case(io_config_frame_parity)
Axi4PeripheralUartParityType_NONE : io_config_frame_parity_string = "NONE";
Axi4PeripheralUartParityType_EVEN : io_config_frame_parity_string = "EVEN";
Axi4PeripheralUartParityType_ODD : io_config_frame_parity_string = "ODD ";
default : io_config_frame_parity_string = "????";
endcase
end
`endif
assign clockDivider_tick = (clockDivider_counter == 20'h0);
always @(*) begin
io_write_thrown_valid = io_write_valid;
if(rx_io_break) begin
io_write_thrown_valid = 1'b0;
end
end
always @(*) begin
io_write_ready = io_write_thrown_ready;
if(rx_io_break) begin
io_write_ready = 1'b1;
end
end
assign io_write_thrown_payload = io_write_payload;
assign io_write_thrown_ready = tx_io_write_ready;
assign io_read_valid = rx_io_read_valid;
assign io_read_payload = rx_io_read_payload;
assign io_uart_txd = tx_io_txd;
assign io_readError = rx_io_error;
assign io_readBreak = rx_io_break;
always @(posedge clk) begin
if(reset) begin
clockDivider_counter <= 20'h0;
clockDivider_tickReg <= 1'b0;
end else begin
clockDivider_tickReg <= clockDivider_tick;
clockDivider_counter <= (clockDivider_counter - 20'h00001);
if(clockDivider_tick) begin
clockDivider_counter <= io_config_clockDivider;
end
end
end
endmodule
module Axi4PeripheralUartCtrlRx_86b7e1c47b934a8a97a62bda8ee6a75d (
input wire [2:0] io_configFrame_dataLength,
input wire [0:0] io_configFrame_stop,
input wire [1:0] io_configFrame_parity,
input wire io_samplingTick,
output wire io_read_valid,
input wire io_read_ready,
output wire [7:0] io_read_payload,
input wire io_rxd,
output wire io_rts,
output reg io_error,
output wire io_break,
input wire clk,
input wire reset
);
localparam Axi4PeripheralUartStopType_ONE = 1'd0;
localparam Axi4PeripheralUartStopType_TWO = 1'd1;
localparam Axi4PeripheralUartParityType_NONE = 2'd0;
localparam Axi4PeripheralUartParityType_EVEN = 2'd1;
localparam Axi4PeripheralUartParityType_ODD = 2'd2;
localparam Axi4PeripheralUartCtrlRxState_IDLE = 3'd0;
localparam Axi4PeripheralUartCtrlRxState_START = 3'd1;
localparam Axi4PeripheralUartCtrlRxState_DATA = 3'd2;
localparam Axi4PeripheralUartCtrlRxState_PARITY = 3'd3;
localparam Axi4PeripheralUartCtrlRxState_STOP = 3'd4;
wire io_rxd_buffercc_io_dataOut;
wire _zz_sampler_value;
wire _zz_sampler_value_1;
wire _zz_sampler_value_2;
wire _zz_sampler_value_3;
wire _zz_sampler_value_4;
wire _zz_sampler_value_5;
wire _zz_sampler_value_6;
wire [2:0] _zz_when_UartCtrlRx_l139;
wire [0:0] _zz_when_UartCtrlRx_l139_1;
reg _zz_io_rts;
wire sampler_synchroniser;
wire sampler_samples_0;
reg sampler_samples_1;
reg sampler_samples_2;
reg sampler_samples_3;
reg sampler_samples_4;
reg sampler_value;
reg sampler_tick;
reg [2:0] bitTimer_counter;
reg bitTimer_tick;
wire when_UartCtrlRx_l43;
reg [2:0] bitCounter_value;
reg [6:0] break_counter;
wire break_valid;
wire when_UartCtrlRx_l69;
reg [2:0] stateMachine_state;
reg stateMachine_parity;
reg [7:0] stateMachine_shifter;
reg stateMachine_validReg;
wire when_UartCtrlRx_l93;
wire when_UartCtrlRx_l103;
wire when_UartCtrlRx_l111;
wire when_UartCtrlRx_l113;
wire when_UartCtrlRx_l125;
wire when_UartCtrlRx_l136;
wire when_UartCtrlRx_l139;
`ifndef SYNTHESIS
reg [23:0] io_configFrame_stop_string;
reg [31:0] io_configFrame_parity_string;
reg [47:0] stateMachine_state_string;
`endif
assign _zz_when_UartCtrlRx_l139_1 = ((io_configFrame_stop == Axi4PeripheralUartStopType_ONE) ? 1'b0 : 1'b1);
assign _zz_when_UartCtrlRx_l139 = {2'd0, _zz_when_UartCtrlRx_l139_1};
assign _zz_sampler_value = ((((1'b0 || ((_zz_sampler_value_1 && sampler_samples_1) && sampler_samples_2)) || (((_zz_sampler_value_2 && sampler_samples_0) && sampler_samples_1) && sampler_samples_3)) || (((1'b1 && sampler_samples_0) && sampler_samples_2) && sampler_samples_3)) || (((1'b1 && sampler_samples_1) && sampler_samples_2) && sampler_samples_3));
assign _zz_sampler_value_3 = (((1'b1 && sampler_samples_0) && sampler_samples_1) && sampler_samples_4);
assign _zz_sampler_value_4 = ((1'b1 && sampler_samples_0) && sampler_samples_2);
assign _zz_sampler_value_5 = (1'b1 && sampler_samples_1);
assign _zz_sampler_value_6 = 1'b1;
assign _zz_sampler_value_1 = (1'b1 && sampler_samples_0);
assign _zz_sampler_value_2 = 1'b1;
(* keep_hierarchy = "TRUE" *) Axi4PeripheralBufferCC_86b7e1c47b934a8a97a62bda8ee6a75d io_rxd_buffercc (
.io_dataIn (io_rxd ), //i
.io_dataOut (io_rxd_buffercc_io_dataOut), //o
.clk (clk ), //i
.reset (reset ) //i
);
`ifndef SYNTHESIS
always @(*) begin
case(io_configFrame_stop)
Axi4PeripheralUartStopType_ONE : io_configFrame_stop_string = "ONE";
Axi4PeripheralUartStopType_TWO : io_configFrame_stop_string = "TWO";
default : io_configFrame_stop_string = "???";
endcase
end
always @(*) begin
case(io_configFrame_parity)
Axi4PeripheralUartParityType_NONE : io_configFrame_parity_string = "NONE";
Axi4PeripheralUartParityType_EVEN : io_configFrame_parity_string = "EVEN";
Axi4PeripheralUartParityType_ODD : io_configFrame_parity_string = "ODD ";
default : io_configFrame_parity_string = "????";
endcase
end
always @(*) begin
case(stateMachine_state)
Axi4PeripheralUartCtrlRxState_IDLE : stateMachine_state_string = "IDLE ";
Axi4PeripheralUartCtrlRxState_START : stateMachine_state_string = "START ";
Axi4PeripheralUartCtrlRxState_DATA : stateMachine_state_string = "DATA ";
Axi4PeripheralUartCtrlRxState_PARITY : stateMachine_state_string = "PARITY";
Axi4PeripheralUartCtrlRxState_STOP : stateMachine_state_string = "STOP ";
default : stateMachine_state_string = "??????";
endcase
end
`endif
always @(*) begin
io_error = 1'b0;
case(stateMachine_state)
Axi4PeripheralUartCtrlRxState_IDLE : begin
end
Axi4PeripheralUartCtrlRxState_START : begin
end
Axi4PeripheralUartCtrlRxState_DATA : begin
end
Axi4PeripheralUartCtrlRxState_PARITY : begin
if(bitTimer_tick) begin
if(!when_UartCtrlRx_l125) begin
io_error = 1'b1;
end
end
end
default : begin
if(bitTimer_tick) begin
if(when_UartCtrlRx_l136) begin
io_error = 1'b1;
end
end
end
endcase
end
assign io_rts = _zz_io_rts;
assign sampler_synchroniser = io_rxd_buffercc_io_dataOut;
assign sampler_samples_0 = sampler_synchroniser;
always @(*) begin
bitTimer_tick = 1'b0;
if(sampler_tick) begin
if(when_UartCtrlRx_l43) begin
bitTimer_tick = 1'b1;
end
end
end
assign when_UartCtrlRx_l43 = (bitTimer_counter == 3'b000);
assign break_valid = (break_counter == 7'h68);
assign when_UartCtrlRx_l69 = (io_samplingTick && (! break_valid));
assign io_break = break_valid;
assign io_read_valid = stateMachine_validReg;
assign when_UartCtrlRx_l93 = ((sampler_tick && (! sampler_value)) && (! break_valid));
assign when_UartCtrlRx_l103 = (sampler_value == 1'b1);
assign when_UartCtrlRx_l111 = (bitCounter_value == io_configFrame_dataLength);
assign when_UartCtrlRx_l113 = (io_configFrame_parity == Axi4PeripheralUartParityType_NONE);
assign when_UartCtrlRx_l125 = (stateMachine_parity == sampler_value);
assign when_UartCtrlRx_l136 = (! sampler_value);
assign when_UartCtrlRx_l139 = (bitCounter_value == _zz_when_UartCtrlRx_l139);
assign io_read_payload = stateMachine_shifter;
always @(posedge clk) begin
if(reset) begin
_zz_io_rts <= 1'b0;
sampler_samples_1 <= 1'b1;
sampler_samples_2 <= 1'b1;
sampler_samples_3 <= 1'b1;
sampler_samples_4 <= 1'b1;
sampler_value <= 1'b1;
sampler_tick <= 1'b0;
break_counter <= 7'h0;
stateMachine_state <= Axi4PeripheralUartCtrlRxState_IDLE;
stateMachine_validReg <= 1'b0;
end else begin
_zz_io_rts <= (! io_read_ready);
if(io_samplingTick) begin
sampler_samples_1 <= sampler_samples_0;
end
if(io_samplingTick) begin
sampler_samples_2 <= sampler_samples_1;
end
if(io_samplingTick) begin
sampler_samples_3 <= sampler_samples_2;
end
if(io_samplingTick) begin
sampler_samples_4 <= sampler_samples_3;
end
sampler_value <= ((((((_zz_sampler_value || _zz_sampler_value_3) || (_zz_sampler_value_4 && sampler_samples_4)) || ((_zz_sampler_value_5 && sampler_samples_2) && sampler_samples_4)) || (((_zz_sampler_value_6 && sampler_samples_0) && sampler_samples_3) && sampler_samples_4)) || (((1'b1 && sampler_samples_1) && sampler_samples_3) && sampler_samples_4)) || (((1'b1 && sampler_samples_2) && sampler_samples_3) && sampler_samples_4));
sampler_tick <= io_samplingTick;
if(sampler_value) begin
break_counter <= 7'h0;
end else begin
if(when_UartCtrlRx_l69) begin
break_counter <= (break_counter + 7'h01);
end
end
stateMachine_validReg <= 1'b0;
case(stateMachine_state)
Axi4PeripheralUartCtrlRxState_IDLE : begin
if(when_UartCtrlRx_l93) begin
stateMachine_state <= Axi4PeripheralUartCtrlRxState_START;
end
end
Axi4PeripheralUartCtrlRxState_START : begin
if(bitTimer_tick) begin
stateMachine_state <= Axi4PeripheralUartCtrlRxState_DATA;
if(when_UartCtrlRx_l103) begin
stateMachine_state <= Axi4PeripheralUartCtrlRxState_IDLE;
end
end
end
Axi4PeripheralUartCtrlRxState_DATA : begin
if(bitTimer_tick) begin
if(when_UartCtrlRx_l111) begin
if(when_UartCtrlRx_l113) begin
stateMachine_state <= Axi4PeripheralUartCtrlRxState_STOP;
stateMachine_validReg <= 1'b1;
end else begin
stateMachine_state <= Axi4PeripheralUartCtrlRxState_PARITY;
end
end
end
end
Axi4PeripheralUartCtrlRxState_PARITY : begin
if(bitTimer_tick) begin
if(when_UartCtrlRx_l125) begin
stateMachine_state <= Axi4PeripheralUartCtrlRxState_STOP;
stateMachine_validReg <= 1'b1;
end else begin
stateMachine_state <= Axi4PeripheralUartCtrlRxState_IDLE;
end
end
end
default : begin
if(bitTimer_tick) begin
if(when_UartCtrlRx_l136) begin
stateMachine_state <= Axi4PeripheralUartCtrlRxState_IDLE;
end else begin
if(when_UartCtrlRx_l139) begin
stateMachine_state <= Axi4PeripheralUartCtrlRxState_IDLE;
end
end
end
end
endcase
end
end
always @(posedge clk) begin
if(sampler_tick) begin
bitTimer_counter <= (bitTimer_counter - 3'b001);
end
if(bitTimer_tick) begin
bitCounter_value <= (bitCounter_value + 3'b001);
end
if(bitTimer_tick) begin
stateMachine_parity <= (stateMachine_parity ^ sampler_value);
end
case(stateMachine_state)
Axi4PeripheralUartCtrlRxState_IDLE : begin
if(when_UartCtrlRx_l93) begin
bitTimer_counter <= 3'b010;
end
end
Axi4PeripheralUartCtrlRxState_START : begin
if(bitTimer_tick) begin
bitCounter_value <= 3'b000;
stateMachine_parity <= (io_configFrame_parity == Axi4PeripheralUartParityType_ODD);
end
end
Axi4PeripheralUartCtrlRxState_DATA : begin
if(bitTimer_tick) begin
stateMachine_shifter[bitCounter_value] <= sampler_value;
if(when_UartCtrlRx_l111) begin
bitCounter_value <= 3'b000;
end
end
end
Axi4PeripheralUartCtrlRxState_PARITY : begin
if(bitTimer_tick) begin
bitCounter_value <= 3'b000;
end
end
default : begin
end
endcase
end
endmodule
module Axi4PeripheralUartCtrlTx_86b7e1c47b934a8a97a62bda8ee6a75d (
input wire [2:0] io_configFrame_dataLength,
input wire [0:0] io_configFrame_stop,
input wire [1:0] io_configFrame_parity,
input wire io_samplingTick,
input wire io_write_valid,
output reg io_write_ready,
input wire [7:0] io_write_payload,
input wire io_cts,
output wire io_txd,
input wire io_break,
input wire clk,
input wire reset
);
localparam Axi4PeripheralUartStopType_ONE = 1'd0;
localparam Axi4PeripheralUartStopType_TWO = 1'd1;
localparam Axi4PeripheralUartParityType_NONE = 2'd0;
localparam Axi4PeripheralUartParityType_EVEN = 2'd1;
localparam Axi4PeripheralUartParityType_ODD = 2'd2;
localparam Axi4PeripheralUartCtrlTxState_IDLE = 3'd0;
localparam Axi4PeripheralUartCtrlTxState_START = 3'd1;
localparam Axi4PeripheralUartCtrlTxState_DATA = 3'd2;
localparam Axi4PeripheralUartCtrlTxState_PARITY = 3'd3;
localparam Axi4PeripheralUartCtrlTxState_STOP = 3'd4;
wire [2:0] _zz_clockDivider_counter_valueNext;
wire [0:0] _zz_clockDivider_counter_valueNext_1;
wire [2:0] _zz_when_UartCtrlTx_l93;
wire [0:0] _zz_when_UartCtrlTx_l93_1;
reg clockDivider_counter_willIncrement;
wire clockDivider_counter_willClear;
reg [2:0] clockDivider_counter_valueNext;
reg [2:0] clockDivider_counter_value;
wire clockDivider_counter_willOverflowIfInc;
wire clockDivider_counter_willOverflow;
reg [2:0] tickCounter_value;
reg [2:0] stateMachine_state;
reg stateMachine_parity;
reg stateMachine_txd;
wire when_UartCtrlTx_l58;
wire when_UartCtrlTx_l73;
wire when_UartCtrlTx_l76;
wire when_UartCtrlTx_l93;
wire [2:0] _zz_stateMachine_state;
reg _zz_io_txd;
`ifndef SYNTHESIS
reg [23:0] io_configFrame_stop_string;
reg [31:0] io_configFrame_parity_string;
reg [47:0] stateMachine_state_string;
reg [47:0] _zz_stateMachine_state_string;
`endif
assign _zz_clockDivider_counter_valueNext_1 = clockDivider_counter_willIncrement;
assign _zz_clockDivider_counter_valueNext = {2'd0, _zz_clockDivider_counter_valueNext_1};
assign _zz_when_UartCtrlTx_l93_1 = ((io_configFrame_stop == Axi4PeripheralUartStopType_ONE) ? 1'b0 : 1'b1);
assign _zz_when_UartCtrlTx_l93 = {2'd0, _zz_when_UartCtrlTx_l93_1};
`ifndef SYNTHESIS
always @(*) begin
case(io_configFrame_stop)
Axi4PeripheralUartStopType_ONE : io_configFrame_stop_string = "ONE";
Axi4PeripheralUartStopType_TWO : io_configFrame_stop_string = "TWO";
default : io_configFrame_stop_string = "???";
endcase
end
always @(*) begin
case(io_configFrame_parity)
Axi4PeripheralUartParityType_NONE : io_configFrame_parity_string = "NONE";
Axi4PeripheralUartParityType_EVEN : io_configFrame_parity_string = "EVEN";
Axi4PeripheralUartParityType_ODD : io_configFrame_parity_string = "ODD ";
default : io_configFrame_parity_string = "????";
endcase
end
always @(*) begin
case(stateMachine_state)
Axi4PeripheralUartCtrlTxState_IDLE : stateMachine_state_string = "IDLE ";
Axi4PeripheralUartCtrlTxState_START : stateMachine_state_string = "START ";
Axi4PeripheralUartCtrlTxState_DATA : stateMachine_state_string = "DATA ";
Axi4PeripheralUartCtrlTxState_PARITY : stateMachine_state_string = "PARITY";
Axi4PeripheralUartCtrlTxState_STOP : stateMachine_state_string = "STOP ";
default : stateMachine_state_string = "??????";
endcase
end
always @(*) begin
case(_zz_stateMachine_state)
Axi4PeripheralUartCtrlTxState_IDLE : _zz_stateMachine_state_string = "IDLE ";
Axi4PeripheralUartCtrlTxState_START : _zz_stateMachine_state_string = "START ";
Axi4PeripheralUartCtrlTxState_DATA : _zz_stateMachine_state_string = "DATA ";
Axi4PeripheralUartCtrlTxState_PARITY : _zz_stateMachine_state_string = "PARITY";
Axi4PeripheralUartCtrlTxState_STOP : _zz_stateMachine_state_string = "STOP ";
default : _zz_stateMachine_state_string = "??????";
endcase
end
`endif
always @(*) begin
clockDivider_counter_willIncrement = 1'b0;
if(io_samplingTick) begin
clockDivider_counter_willIncrement = 1'b1;
end
end
assign clockDivider_counter_willClear = 1'b0;
assign clockDivider_counter_willOverflowIfInc = (clockDivider_counter_value == 3'b111);
assign clockDivider_counter_willOverflow = (clockDivider_counter_willOverflowIfInc && clockDivider_counter_willIncrement);
always @(*) begin
clockDivider_counter_valueNext = (clockDivider_counter_value + _zz_clockDivider_counter_valueNext);
if(clockDivider_counter_willClear) begin
clockDivider_counter_valueNext = 3'b000;
end
end
always @(*) begin
stateMachine_txd = 1'b1;
case(stateMachine_state)
Axi4PeripheralUartCtrlTxState_IDLE : begin
end
Axi4PeripheralUartCtrlTxState_START : begin
stateMachine_txd = 1'b0;
end
Axi4PeripheralUartCtrlTxState_DATA : begin
stateMachine_txd = io_write_payload[tickCounter_value];
end
Axi4PeripheralUartCtrlTxState_PARITY : begin
stateMachine_txd = stateMachine_parity;
end
default : begin
end
endcase
end
always @(*) begin
io_write_ready = io_break;
case(stateMachine_state)
Axi4PeripheralUartCtrlTxState_IDLE : begin
end
Axi4PeripheralUartCtrlTxState_START : begin
end
Axi4PeripheralUartCtrlTxState_DATA : begin
if(clockDivider_counter_willOverflow) begin
if(when_UartCtrlTx_l73) begin
io_write_ready = 1'b1;
end
end
end
Axi4PeripheralUartCtrlTxState_PARITY : begin
end
default : begin
end
endcase
end
assign when_UartCtrlTx_l58 = ((io_write_valid && (! io_cts)) && clockDivider_counter_willOverflow);
assign when_UartCtrlTx_l73 = (tickCounter_value == io_configFrame_dataLength);
assign when_UartCtrlTx_l76 = (io_configFrame_parity == Axi4PeripheralUartParityType_NONE);
assign when_UartCtrlTx_l93 = (tickCounter_value == _zz_when_UartCtrlTx_l93);
assign _zz_stateMachine_state = (io_write_valid ? Axi4PeripheralUartCtrlTxState_START : Axi4PeripheralUartCtrlTxState_IDLE);
assign io_txd = _zz_io_txd;
always @(posedge clk) begin
if(reset) begin
clockDivider_counter_value <= 3'b000;
stateMachine_state <= Axi4PeripheralUartCtrlTxState_IDLE;
_zz_io_txd <= 1'b1;
end else begin
clockDivider_counter_value <= clockDivider_counter_valueNext;
case(stateMachine_state)
Axi4PeripheralUartCtrlTxState_IDLE : begin
if(when_UartCtrlTx_l58) begin
stateMachine_state <= Axi4PeripheralUartCtrlTxState_START;
end
end
Axi4PeripheralUartCtrlTxState_START : begin
if(clockDivider_counter_willOverflow) begin
stateMachine_state <= Axi4PeripheralUartCtrlTxState_DATA;
end
end
Axi4PeripheralUartCtrlTxState_DATA : begin
if(clockDivider_counter_willOverflow) begin
if(when_UartCtrlTx_l73) begin
if(when_UartCtrlTx_l76) begin
stateMachine_state <= Axi4PeripheralUartCtrlTxState_STOP;
end else begin
stateMachine_state <= Axi4PeripheralUartCtrlTxState_PARITY;
end
end
end
end
Axi4PeripheralUartCtrlTxState_PARITY : begin
if(clockDivider_counter_willOverflow) begin
stateMachine_state <= Axi4PeripheralUartCtrlTxState_STOP;
end
end
default : begin
if(clockDivider_counter_willOverflow) begin
if(when_UartCtrlTx_l93) begin
stateMachine_state <= _zz_stateMachine_state;
end
end
end
endcase
_zz_io_txd <= (stateMachine_txd && (! io_break));
end
end
always @(posedge clk) begin
if(clockDivider_counter_willOverflow) begin
tickCounter_value <= (tickCounter_value + 3'b001);
end
if(clockDivider_counter_willOverflow) begin
stateMachine_parity <= (stateMachine_parity ^ stateMachine_txd);
end
case(stateMachine_state)
Axi4PeripheralUartCtrlTxState_IDLE : begin
end
Axi4PeripheralUartCtrlTxState_START : begin
if(clockDivider_counter_willOverflow) begin
stateMachine_parity <= (io_configFrame_parity == Axi4PeripheralUartParityType_ODD);
tickCounter_value <= 3'b000;
end
end
Axi4PeripheralUartCtrlTxState_DATA : begin
if(clockDivider_counter_willOverflow) begin
if(when_UartCtrlTx_l73) begin
tickCounter_value <= 3'b000;
end
end
end
Axi4PeripheralUartCtrlTxState_PARITY : begin
if(clockDivider_counter_willOverflow) begin
tickCounter_value <= 3'b000;
end
end
default : begin
end
endcase
end
endmodule
module Axi4PeripheralBufferCC_86b7e1c47b934a8a97a62bda8ee6a75d (
input wire io_dataIn,
output wire io_dataOut,
input wire clk,
input wire reset
);
(* async_reg = "true" *) reg buffers_0;
(* async_reg = "true" *) reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge clk) begin
if(reset) begin
buffers_0 <= 1'b0;
buffers_1 <= 1'b0;
end else begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
end
endmodule
`undef IP_UUID
`undef IP_NAME_CONCAT
`undef IP_MODULE_NAME
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