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wireguard_fpga/Ti375C529_devkit/Ti375C529_devkit.isf
Byron Lathi 2f2727777b Start work on parser
2026-08-13 08:35:49 -07:00

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# Efinity Interface Configuration
# Version: 2025.2.288.2.10
# Date: 2026-08-09 19:10
#
# Copyright (C) 2013 - 2025 Efinix Inc. All rights reserved.
#
# Device: Ti375C529
# Package: 529-ball FBGA (final)
# Project: Ti375C529_devkit
# Configuration mode: active (x1)
# Timing Model: C4 (final)
# Device setting
design.set_device_property("2A","DYNAMIC_VOLTAGE","0","IOBANK")
design.set_mode_sel_name("2A","2A_MODE_SEL","2A")
design.set_device_property("2A","VOLTAGE","1.8","IOBANK")
design.set_device_property("2B","DYNAMIC_VOLTAGE","0","IOBANK")
design.set_mode_sel_name("2B","2B_MODE_SEL","2B")
design.set_device_property("2B","VOLTAGE","1.8","IOBANK")
design.set_device_property("2C","DYNAMIC_VOLTAGE","0","IOBANK")
design.set_mode_sel_name("2C","2C_MODE_SEL","2C")
design.set_device_property("2C","VOLTAGE","1.8","IOBANK")
design.set_device_property("2D","DYNAMIC_VOLTAGE","0","IOBANK")
design.set_mode_sel_name("2D","2D_MODE_SEL","2D")
design.set_device_property("2D","VOLTAGE","1.8","IOBANK")
design.set_device_property("2E","DYNAMIC_VOLTAGE","0","IOBANK")
design.set_mode_sel_name("2E","2E_MODE_SEL","2E")
design.set_device_property("2E","VOLTAGE","1.8","IOBANK")
design.set_device_property("4A_4B","DYNAMIC_VOLTAGE","0","IOBANK")
design.set_mode_sel_name("4A_4B","4A_4B_MODE_SEL","4A_4B")
design.set_device_property("4A_4B","VOLTAGE","1.8","IOBANK")
design.set_device_property("4C","DYNAMIC_VOLTAGE","0","IOBANK")
design.set_mode_sel_name("4C","4C_MODE_SEL","4C")
design.set_device_property("4C","VOLTAGE","1.8","IOBANK")
design.set_device_property("4D","DYNAMIC_VOLTAGE","0","IOBANK")
design.set_mode_sel_name("4D","4D_MODE_SEL","4D")
design.set_device_property("4D","VOLTAGE","1.8","IOBANK")
design.set_device_property("BL2_BL3","DYNAMIC_VOLTAGE","0","IOBANK")
design.set_mode_sel_name("BL2_BL3","BL2_BL3_MODE_SEL","BL2_BL3")
design.set_device_property("BL2_BL3","VOLTAGE","3.3","IOBANK")
design.set_device_property("BR0","DYNAMIC_VOLTAGE","0","IOBANK")
design.set_mode_sel_name("BR0","BR0_MODE_SEL","BR0")
design.set_device_property("BR0","VOLTAGE","3.3","IOBANK")
design.set_device_property("BR3_BR4","DYNAMIC_VOLTAGE","0","IOBANK")
design.set_mode_sel_name("BR3_BR4","BR3_BR4_MODE_SEL","BR3_BR4")
design.set_device_property("BR3_BR4","VOLTAGE","3.3","IOBANK")
design.set_device_property("TL1_TL5","DYNAMIC_VOLTAGE","0","IOBANK")
design.set_mode_sel_name("TL1_TL5","TL1_TL5_MODE_SEL","TL1_TL5")
design.set_device_property("TL1_TL5","VOLTAGE","3.3","IOBANK")
design.set_device_property("TR0","DYNAMIC_VOLTAGE","0","IOBANK")
design.set_mode_sel_name("TR0","TR0_MODE_SEL","TR0")
design.set_device_property("TR0","VOLTAGE","3.3","IOBANK")
design.set_device_property("TR1","DYNAMIC_VOLTAGE","0","IOBANK")
design.set_mode_sel_name("TR1","TR1_MODE_SEL","TR1")
design.set_device_property("TR1","VOLTAGE","3.3","IOBANK")
design.set_device_property("TR2","DYNAMIC_VOLTAGE","0","IOBANK")
design.set_mode_sel_name("TR2","TR2_MODE_SEL","TR2")
design.set_device_property("TR2","VOLTAGE","3.3","IOBANK")
design.set_device_property("seu","ENA_DETECT","0","SEU")
design.set_device_property("cfg","CBSEL_PIN","cfg_CBSEL","RU")
design.set_device_property("cfg","CLK_PIN","","RU")
design.set_device_property("cfg","CONFIG_PIN","cfg_CONFIG","RU")
design.set_device_property("cfg","ENA_PIN","cfg_ENA","RU")
design.set_device_property("cfg","ERROR_PIN","cfg_ERROR","RU")
design.set_device_property("cfg","INVERT_CLK_EN","0","RU")
design.set_device_property("cfg","RECONFIG_EN","0","RU")
design.set_device_property("cfg","REMOTE_UPDATE_RETRIES","3","RU")
design.set_device_property("Bottom","CORE0_PIN","","CLKMUX")
design.set_device_property("Bottom","CORE1_PIN","","CLKMUX")
design.set_device_property("Bottom","CORE2_PIN","","CLKMUX")
design.set_device_property("Bottom","CORE3_PIN","","CLKMUX")
design.set_device_property("Bottom","DYN_MUX0_EN","0","CLKMUX")
design.set_device_property("Bottom","DYN_MUX7_EN","0","CLKMUX")
design.set_device_property("Left","CORE0_PIN","","CLKMUX")
design.set_device_property("Left","CORE1_PIN","","CLKMUX")
design.set_device_property("Left","CORE2_PIN","","CLKMUX")
design.set_device_property("Left","CORE3_PIN","","CLKMUX")
design.set_device_property("Left","DYN_MUX0_EN","0","CLKMUX")
design.set_device_property("Left","DYN_MUX7_EN","0","CLKMUX")
design.set_device_property("Right","CORE0_PIN","","CLKMUX")
design.set_device_property("Right","CORE1_PIN","","CLKMUX")
design.set_device_property("Right","CORE2_PIN","","CLKMUX")
design.set_device_property("Right","CORE3_PIN","","CLKMUX")
design.set_device_property("Right","DYN_MUX0_EN","0","CLKMUX")
design.set_device_property("Right","DYN_MUX7_EN","0","CLKMUX")
design.set_device_property("Top","CORE0_PIN","","CLKMUX")
design.set_device_property("Top","CORE1_PIN","","CLKMUX")
design.set_device_property("Top","CORE2_PIN","","CLKMUX")
design.set_device_property("Top","CORE3_PIN","","CLKMUX")
design.set_device_property("Top","DYN_MUX0_EN","0","CLKMUX")
design.set_device_property("Top","DYN_MUX7_EN","0","CLKMUX")
# Create instance
design.create_block("soc_jtag_inst1","JTAG")
design.create_block("qcrv32_inst1","SOC")
# Set property, non-defaults
design.set_property("soc_jtag_inst1","NAME","soc_jtag_inst1","JTAG")
design.set_property("soc_jtag_inst1","RESOURCE","JTAG_USER1","JTAG")
design.set_property("soc_jtag_inst1","CAPTURE","ut_jtagCtrl_capture","JTAG")
design.set_property("soc_jtag_inst1","DRCK","","JTAG")
design.set_property("soc_jtag_inst1","RESET","ut_jtagCtrl_reset","JTAG")
design.set_property("soc_jtag_inst1","RUNTEST","","JTAG")
design.set_property("soc_jtag_inst1","SEL","ut_jtagCtrl_enable","JTAG")
design.set_property("soc_jtag_inst1","SHIFT","ut_jtagCtrl_shift","JTAG")
design.set_property("soc_jtag_inst1","TCK","jtagCtrl_tck","JTAG")
design.set_property("soc_jtag_inst1","TDI","ut_jtagCtrl_tdi","JTAG")
design.set_property("soc_jtag_inst1","TMS","","JTAG")
design.set_property("soc_jtag_inst1","UPDATE","ut_jtagCtrl_update","JTAG")
design.set_property("soc_jtag_inst1","TDO","ut_jtagCtrl_tdo","JTAG")
design.set_property("qcrv32_inst1","AXIAINTERRUPT_PIN","axiAInterrupt","SOC")
design.set_property("qcrv32_inst1","AXIA_ARADDR_PIN","axiA_araddr","SOC")
design.set_property("qcrv32_inst1","AXIA_ARBURST_PIN","axiA_arburst","SOC")
design.set_property("qcrv32_inst1","AXIA_ARCACHE_PIN","axiA_arcache","SOC")
design.set_property("qcrv32_inst1","AXIA_ARLEN_PIN","axiA_arlen","SOC")
design.set_property("qcrv32_inst1","AXIA_ARLOCK_PIN","axiA_arlock","SOC")
design.set_property("qcrv32_inst1","AXIA_ARPROT_PIN","axiA_arprot","SOC")
design.set_property("qcrv32_inst1","AXIA_ARQOS_PIN","axiA_arqos","SOC")
design.set_property("qcrv32_inst1","AXIA_ARREADY_PIN","axiA_arready","SOC")
design.set_property("qcrv32_inst1","AXIA_ARREGION_PIN","axiA_arregion","SOC")
design.set_property("qcrv32_inst1","AXIA_ARSIZE_PIN","axiA_arsize","SOC")
design.set_property("qcrv32_inst1","AXIA_ARVALID_PIN","axiA_arvalid","SOC")
design.set_property("qcrv32_inst1","AXIA_AWADDR_PIN","axiA_awaddr","SOC")
design.set_property("qcrv32_inst1","AXIA_AWBURST_PIN","axiA_awburst","SOC")
design.set_property("qcrv32_inst1","AXIA_AWCACHE_PIN","axiA_awcache","SOC")
design.set_property("qcrv32_inst1","AXIA_AWLEN_PIN","axiA_awlen","SOC")
design.set_property("qcrv32_inst1","AXIA_AWLOCK_PIN","axiA_awlock","SOC")
design.set_property("qcrv32_inst1","AXIA_AWPROT_PIN","axiA_awprot","SOC")
design.set_property("qcrv32_inst1","AXIA_AWQOS_PIN","axiA_awqos","SOC")
design.set_property("qcrv32_inst1","AXIA_AWREADY_PIN","axiA_awready","SOC")
design.set_property("qcrv32_inst1","AXIA_AWREGION_PIN","axiA_awregion","SOC")
design.set_property("qcrv32_inst1","AXIA_AWSIZE_PIN","axiA_awsize","SOC")
design.set_property("qcrv32_inst1","AXIA_AWVALID_PIN","axiA_awvalid","SOC")
design.set_property("qcrv32_inst1","AXIA_BREADY_PIN","axiA_bready","SOC")
design.set_property("qcrv32_inst1","AXIA_BRESP_PIN","axiA_bresp","SOC")
design.set_property("qcrv32_inst1","AXIA_BVALID_PIN","axiA_bvalid","SOC")
design.set_property("qcrv32_inst1","AXIA_RDATA_PIN","axiA_rdata","SOC")
design.set_property("qcrv32_inst1","AXIA_RLAST_PIN","axiA_rlast","SOC")
design.set_property("qcrv32_inst1","AXIA_RREADY_PIN","axiA_rready","SOC")
design.set_property("qcrv32_inst1","AXIA_RRESP_PIN","axiA_rresp","SOC")
design.set_property("qcrv32_inst1","AXIA_RVALID_PIN","axiA_rvalid","SOC")
design.set_property("qcrv32_inst1","AXIA_WDATA_PIN","axiA_wdata","SOC")
design.set_property("qcrv32_inst1","AXIA_WLAST_PIN","axiA_wlast","SOC")
design.set_property("qcrv32_inst1","AXIA_WREADY_PIN","axiA_wready","SOC")
design.set_property("qcrv32_inst1","AXIA_WSTRB_PIN","axiA_wstrb","SOC")
design.set_property("qcrv32_inst1","AXIA_WVALID_PIN","axiA_wvalid","SOC")
design.set_property("qcrv32_inst1","AXI_MASTER_EN","1","SOC")
design.set_property("qcrv32_inst1","AXI_SLAVE_EN","1","SOC")
design.set_property("qcrv32_inst1","CPU0_CUSTOMINSTRUCTION_CMD_READY_PIN","cpu0_customInstruction_cmd_ready","SOC")
design.set_property("qcrv32_inst1","CPU0_CUSTOMINSTRUCTION_CMD_VALID_PIN","cpu0_customInstruction_cmd_valid","SOC")
design.set_property("qcrv32_inst1","CPU0_CUSTOMINSTRUCTION_FUNCTION_ID_PIN","cpu0_customInstruction_function_id","SOC")
design.set_property("qcrv32_inst1","CPU0_CUSTOMINSTRUCTION_INPUTS_0_PIN","cpu0_customInstruction_inputs_0","SOC")
design.set_property("qcrv32_inst1","CPU0_CUSTOMINSTRUCTION_INPUTS_1_PIN","cpu0_customInstruction_inputs_1","SOC")
design.set_property("qcrv32_inst1","CPU0_CUSTOMINSTRUCTION_OUTPUTS_0_PIN","cpu0_customInstruction_outputs_0","SOC")
design.set_property("qcrv32_inst1","CPU0_CUSTOMINSTRUCTION_RSP_READY_PIN","cpu0_customInstruction_rsp_ready","SOC")
design.set_property("qcrv32_inst1","CPU0_CUSTOMINSTRUCTION_RSP_VALID_PIN","cpu0_customInstruction_rsp_valid","SOC")
design.set_property("qcrv32_inst1","CPU1_CUSTOMINSTRUCTION_CMD_READY_PIN","cpu1_customInstruction_cmd_ready","SOC")
design.set_property("qcrv32_inst1","CPU1_CUSTOMINSTRUCTION_CMD_VALID_PIN","cpu1_customInstruction_cmd_valid","SOC")
design.set_property("qcrv32_inst1","CPU1_CUSTOMINSTRUCTION_FUNCTION_ID_PIN","cpu1_customInstruction_function_id","SOC")
design.set_property("qcrv32_inst1","CPU1_CUSTOMINSTRUCTION_INPUTS_0_PIN","cpu1_customInstruction_inputs_0","SOC")
design.set_property("qcrv32_inst1","CPU1_CUSTOMINSTRUCTION_INPUTS_1_PIN","cpu1_customInstruction_inputs_1","SOC")
design.set_property("qcrv32_inst1","CPU1_CUSTOMINSTRUCTION_OUTPUTS_0_PIN","cpu1_customInstruction_outputs_0","SOC")
design.set_property("qcrv32_inst1","CPU1_CUSTOMINSTRUCTION_RSP_READY_PIN","cpu1_customInstruction_rsp_ready","SOC")
design.set_property("qcrv32_inst1","CPU1_CUSTOMINSTRUCTION_RSP_VALID_PIN","cpu1_customInstruction_rsp_valid","SOC")
design.set_property("qcrv32_inst1","CPU2_CUSTOMINSTRUCTION_CMD_READY_PIN","cpu2_customInstruction_cmd_ready","SOC")
design.set_property("qcrv32_inst1","CPU2_CUSTOMINSTRUCTION_CMD_VALID_PIN","cpu2_customInstruction_cmd_valid","SOC")
design.set_property("qcrv32_inst1","CPU2_CUSTOMINSTRUCTION_FUNCTION_ID_PIN","cpu2_customInstruction_function_id","SOC")
design.set_property("qcrv32_inst1","CPU2_CUSTOMINSTRUCTION_INPUTS_0_PIN","cpu2_customInstruction_inputs_0","SOC")
design.set_property("qcrv32_inst1","CPU2_CUSTOMINSTRUCTION_INPUTS_1_PIN","cpu2_customInstruction_inputs_1","SOC")
design.set_property("qcrv32_inst1","CPU2_CUSTOMINSTRUCTION_OUTPUTS_0_PIN","cpu2_customInstruction_outputs_0","SOC")
design.set_property("qcrv32_inst1","CPU2_CUSTOMINSTRUCTION_RSP_READY_PIN","cpu2_customInstruction_rsp_ready","SOC")
design.set_property("qcrv32_inst1","CPU2_CUSTOMINSTRUCTION_RSP_VALID_PIN","cpu2_customInstruction_rsp_valid","SOC")
design.set_property("qcrv32_inst1","CPU3_CUSTOMINSTRUCTION_CMD_READY_PIN","cpu3_customInstruction_cmd_ready","SOC")
design.set_property("qcrv32_inst1","CPU3_CUSTOMINSTRUCTION_CMD_VALID_PIN","cpu3_customInstruction_cmd_valid","SOC")
design.set_property("qcrv32_inst1","CPU3_CUSTOMINSTRUCTION_FUNCTION_ID_PIN","cpu3_customInstruction_function_id","SOC")
design.set_property("qcrv32_inst1","CPU3_CUSTOMINSTRUCTION_INPUTS_0_PIN","cpu3_customInstruction_inputs_0","SOC")
design.set_property("qcrv32_inst1","CPU3_CUSTOMINSTRUCTION_INPUTS_1_PIN","cpu3_customInstruction_inputs_1","SOC")
design.set_property("qcrv32_inst1","CPU3_CUSTOMINSTRUCTION_OUTPUTS_0_PIN","cpu3_customInstruction_outputs_0","SOC")
design.set_property("qcrv32_inst1","CPU3_CUSTOMINSTRUCTION_RSP_READY_PIN","cpu3_customInstruction_rsp_ready","SOC")
design.set_property("qcrv32_inst1","CPU3_CUSTOMINSTRUCTION_RSP_VALID_PIN","cpu3_customInstruction_rsp_valid","SOC")
design.set_property("qcrv32_inst1","CUSTOM_INSTRUCTION_0_EN","1","SOC")
design.set_property("qcrv32_inst1","CUSTOM_INSTRUCTION_1_EN","1","SOC")
design.set_property("qcrv32_inst1","CUSTOM_INSTRUCTION_2_EN","1","SOC")
design.set_property("qcrv32_inst1","CUSTOM_INSTRUCTION_3_EN","1","SOC")
design.set_property("qcrv32_inst1","IO_ASYNCRESET_PIN","io_asyncReset","SOC")
design.set_property("qcrv32_inst1","IO_CFUCLK_INVERT_EN","0","SOC")
design.set_property("qcrv32_inst1","IO_CFUCLK_PIN","io_cfuClk","SOC")
design.set_property("qcrv32_inst1","IO_CFURESET_PIN","io_cfuReset","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AR_PAYLOAD_ADDR_PIN","io_ddrMasters_0_ar_payload_addr","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AR_PAYLOAD_BURST_PIN","io_ddrMasters_0_ar_payload_burst","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AR_PAYLOAD_CACHE_PIN","io_ddrMasters_0_ar_payload_cache","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AR_PAYLOAD_ID_PIN","io_ddrMasters_0_ar_payload_id","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AR_PAYLOAD_LEN_PIN","io_ddrMasters_0_ar_payload_len","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AR_PAYLOAD_LOCK_PIN","io_ddrMasters_0_ar_payload_lock","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AR_PAYLOAD_PROT_PIN","io_ddrMasters_0_ar_payload_prot","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AR_PAYLOAD_QOS_PIN","io_ddrMasters_0_ar_payload_qos","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AR_PAYLOAD_REGION_PIN","io_ddrMasters_0_ar_payload_region","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AR_PAYLOAD_SIZE_PIN","io_ddrMasters_0_ar_payload_size","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AR_READY_PIN","io_ddrMasters_0_ar_ready","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AR_VALID_PIN","io_ddrMasters_0_ar_valid","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AW_PAYLOAD_ADDR_PIN","io_ddrMasters_0_aw_payload_addr","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AW_PAYLOAD_ALLSTRB_PIN","io_ddrMasters_0_aw_payload_allStrb","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AW_PAYLOAD_BURST_PIN","io_ddrMasters_0_aw_payload_burst","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AW_PAYLOAD_CACHE_PIN","io_ddrMasters_0_aw_payload_cache","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AW_PAYLOAD_ID_PIN","io_ddrMasters_0_aw_payload_id","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AW_PAYLOAD_LEN_PIN","io_ddrMasters_0_aw_payload_len","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AW_PAYLOAD_LOCK_PIN","io_ddrMasters_0_aw_payload_lock","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AW_PAYLOAD_PROT_PIN","io_ddrMasters_0_aw_payload_prot","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AW_PAYLOAD_QOS_PIN","io_ddrMasters_0_aw_payload_qos","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AW_PAYLOAD_REGION_PIN","io_ddrMasters_0_aw_payload_region","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AW_PAYLOAD_SIZE_PIN","io_ddrMasters_0_aw_payload_size","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AW_READY_PIN","io_ddrMasters_0_aw_ready","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AW_VALID_PIN","io_ddrMasters_0_aw_valid","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_B_PAYLOAD_ID_PIN","io_ddrMasters_0_b_payload_id","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_B_PAYLOAD_RESP_PIN","io_ddrMasters_0_b_payload_resp","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_B_READY_PIN","io_ddrMasters_0_b_ready","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_B_VALID_PIN","io_ddrMasters_0_b_valid","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_CLK_INVERT_EN","0","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_CLK_PIN","io_ddrMasters_0_clk","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_RESET_PIN","io_ddrMasters_0_reset","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_R_PAYLOAD_DATA_PIN","io_ddrMasters_0_r_payload_data","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_R_PAYLOAD_ID_PIN","io_ddrMasters_0_r_payload_id","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_R_PAYLOAD_LAST_PIN","io_ddrMasters_0_r_payload_last","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_R_PAYLOAD_RESP_PIN","io_ddrMasters_0_r_payload_resp","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_R_READY_PIN","io_ddrMasters_0_r_ready","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_R_VALID_PIN","io_ddrMasters_0_r_valid","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_W_PAYLOAD_DATA_PIN","io_ddrMasters_0_w_payload_data","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_W_PAYLOAD_LAST_PIN","io_ddrMasters_0_w_payload_last","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_W_PAYLOAD_STRB_PIN","io_ddrMasters_0_w_payload_strb","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_W_READY_PIN","io_ddrMasters_0_w_ready","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_W_VALID_PIN","io_ddrMasters_0_w_valid","SOC")
design.set_property("qcrv32_inst1","IO_JTAG_TCK_INVERT_EN","0","SOC")
design.set_property("qcrv32_inst1","IO_JTAG_TCK_PIN","","SOC")
design.set_property("qcrv32_inst1","IO_JTAG_TDI_PIN","","SOC")
design.set_property("qcrv32_inst1","IO_JTAG_TDO_PIN","","SOC")
design.set_property("qcrv32_inst1","IO_JTAG_TMS_PIN","","SOC")
design.set_property("qcrv32_inst1","IO_PERIPHERALCLK_INVERT_EN","0","SOC")
design.set_property("qcrv32_inst1","IO_PERIPHERALCLK_PIN","io_peripheralClk","SOC")
design.set_property("qcrv32_inst1","IO_PERIPHERALRESET_PIN","io_peripheralReset","SOC")
design.set_property("qcrv32_inst1","IO_SYSTEMRESET_PIN","io_systemReset","SOC")
design.set_property("qcrv32_inst1","JTAGCTRL_CAPTURE_PIN","jtagCtrl_capture","SOC")
design.set_property("qcrv32_inst1","JTAGCTRL_ENABLE_PIN","jtagCtrl_enable","SOC")
design.set_property("qcrv32_inst1","JTAGCTRL_RESET_PIN","jtagCtrl_reset","SOC")
design.set_property("qcrv32_inst1","JTAGCTRL_SHIFT_PIN","jtagCtrl_shift","SOC")
design.set_property("qcrv32_inst1","JTAGCTRL_TCK_INVERT_EN","0","SOC")
design.set_property("qcrv32_inst1","JTAGCTRL_TCK_PIN","jtagCtrl_tck","SOC")
design.set_property("qcrv32_inst1","JTAGCTRL_TDI_PIN","jtagCtrl_tdi","SOC")
design.set_property("qcrv32_inst1","JTAGCTRL_TDO_PIN","jtagCtrl_tdo","SOC")
design.set_property("qcrv32_inst1","JTAGCTRL_UPDATE_PIN","jtagCtrl_update","SOC")
design.set_property("qcrv32_inst1","JTAG_TYPE","FPGA","SOC")
design.set_property("qcrv32_inst1","MEM_CLK_SOURCE","Clock 0","SOC")
design.set_property("qcrv32_inst1","OCR_FILE_PATH","","SOC")
design.set_property("qcrv32_inst1","PIPELINE_SOC_AXI_MEM_INTERFACE_EN","0","SOC")
design.set_property("qcrv32_inst1","SYS_CLK_SOURCE","Clock 0","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTA_PIN","userInterruptA","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTB_PIN","userInterruptB","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTC_PIN","userInterruptC","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTD_PIN","userInterruptD","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTE_PIN","userInterruptE","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTF_PIN","userInterruptF","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTG_PIN","userInterruptG","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTH_PIN","userInterruptH","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTI_PIN","userInterruptI","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTJ_PIN","","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTK_PIN","","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTL_PIN","","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTM_PIN","","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTN_PIN","","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTO_PIN","","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTP_PIN","","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTQ_PIN","","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTR_PIN","","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTS_PIN","","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTT_PIN","","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTU_PIN","","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTV_PIN","","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTW_PIN","","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTX_PIN","","SOC")
design.set_property("qcrv32_inst1","WRITEBUFFER_SOC_AXI_INTERFACE_EN","0","SOC")
# Set resource assignment
design.assign_resource("soc_jtag_inst1","JTAG_USER1","JTAG")
design.assign_resource("qcrv32_inst1","SOC_0","SOC")
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