FORMAL proofs no longer depend on the commercial
  Symbiotic EDA Suite.
More updates to remove unnamed generate blocks
Moved sim_testcases to the sim directory
stepchk source added to the repository, necessary to
  pass the test suite

- Control bits for MM2S made consistent w/ user doc
- Sim now checks DMA copy for 8b, 16b, and bus sizes

- Switched how internal registers were investigated for these test
  benches.  The test benches now depend upon setting a MACRO,
  VBENCH_TB, whereby if the macro is set, the internal values are
  made external for the test bench to analyze.  This should get us
  around the problems associated with Verilator updating how to
  access internal registers every now and then.

  Exceptions to this rule are the RESET and HALT signals.

- FIX: External step commands weren't working with the stopped
  clock, but were forcing the CPU to halt forever.

- FIX: FPU instruction decode, so that they (now) properly
  generate illegal instructions if ever issued with no FPU.
  In hindsight, this should have always been the case, and not
  doing this was a CPU design failure.

- FIX: DBGPORT register access interface is now verified in sim,
  bugs found and fixed.

- FIX: genreport.pl now only reports "terminated" if there are no
  other statuses to the proof.  (SBY will "terminate" engines
  if one passes, so this isn't always an error condition.)

- Previously missed copyright updates to 2023 have been caught and fixed