258 lines
12 KiB
Tcl
258 lines
12 KiB
Tcl
# choose pdk
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# set SYN_PDK GF22
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# set SYN_PDK T12
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# choose synthesis top
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# set SYN_TOP SINGLE_ROUTER
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# set SYN_TOP MESH
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# start
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echo "RUN STARTED AT [date]"
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if { $env(SYN_PDK)=="GF22" } {
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# gf22n
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source tcl_scripts/synth_init_lib.tcl
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} elseif { $env(SYN_PDK)=="T12" } {
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# t12n
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source tcl_scripts/synth_init_library.t12.tcl
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} else {
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exit 1
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}
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#start from the path of Makefile rather than#
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# set saving path of formality file
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set DESIGN_NAME $env(DESIGN_NAME)
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if { $env(SYN_TOP)=="MESH" } {
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# mesh
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set TOP_NAME top_mesh_syn
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set FLIST_NAME flist_mesh.syn.f
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} else {
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# single_router
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set TOP_NAME top_single_router_syn
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set FLIST_NAME flist_single_router.syn.f
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}
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set_svf ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/output/${DESIGN_NAME}.synth.svf
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# setup will be included in .synopsys_dc.setup file
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source ./.synopsys_dc.setup
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###################################################################
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#------------------------Specify the libraries---------------------#
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set_app_var search_path "$search_path ."
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#license is needed#
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if { $env(SYN_PDK)=="GF22" } {
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# gf22n
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set_app_var target_library [concat "$DB(ssg0p45v,m40c)"]
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} elseif { $env(SYN_PDK)=="T12" } {
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# t12n
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set_app_var target_library [concat "$DB(ssg0p72v,125c)"]
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} else {
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exit 1
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}
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#.db, TODO: simplify the way of importing target libs#
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#----designware setting-------#
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set_app_var synthetic_library "dw_foundation.sldb"
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set_dp_smartgen_options -hierarchy -smart_compare true -tp_oper_sel auto -tp_opt_tree auto -brent_kung_adder true -adder_radix auto -inv_out_adder_cell auto -mult_radix4 auto -sop2pos_transformation auto -mult_arch auto -optimize_for area,speed
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#Analyzes DesignWare datapath extraction.#
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set_app_var link_library "* $target_library $synthetic_library"
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#all libs which might be used#
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#------------------------- Read the design ------------------------#
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#----------------------#
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## read
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### in dc_shell: read -format sverilog rtl.sv
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### in tcl shell: read_verilog rtl.v; read_db lib.db
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#---------------------#
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## or analyze+elaborate+WORK dir(default)
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define_design_lib WORK -path ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/WORK
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#can be omitted#
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source tcl_scripts/file_to_list.tcl
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analyze -format sverilog [concat [expand_file_list "$env(PROJ_ROOT)/tb/${FLIST_NAME}"]]
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#analyze HDL source code and save intermediate results named .syn in ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/work dir, which can be used by elaborate directly even without anlyzing; TODO: what does es1y_define.sv mean?#
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elaborate ${TOP_NAME}
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# write_file -hierarchy -format verilog -output output/rvh1.synth.elaborate.v
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#for dbg#
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current_design ${TOP_NAME}
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link
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#not necessary after anal. and elab.?, link lib has been defined before#
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analyze_datapath_extraction -no_autoungroup
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#-------------------- Define the design environment -------------------#
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# set_load 2.2 sout
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# set_load 1.5 cout
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# set_driving_cell -lib_cell FD1 [all_inputs]
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#---------------------- Set the design constraints --------------------#
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## Design Rule constraints
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# set_max_transistion
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# set_max_fanout
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# set_max_capacitance
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#provided by foundary company, can be setted tightly in advance; TODO: get precise indicators#
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## Set the optimization constraints
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#----delay----#
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#----area-----#
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set_host_options -max_cores 16
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source tcl_scripts/constraints.sdc
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set_clock_transition 0.1 [all_clocks]
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set_critical_range 10 [current_design]
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group_path -weight 0.1 -name input_path -from [all_inputs]
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group_path -weight 0.1 -name output_path -to [all_outputs]
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group_path -weight 0.1 -name in2out -from [all_inputs] -to [all_outputs]
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set_dynamic_optimization false
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set_leakage_optimization false
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set compile_timing_high_effort true
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set placer_tns_driven true
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set psynopt_tns_high_effort true
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set compile_timing_high_effort_tns true
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set_cost_priority -delay
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puts "TIMESTAMP Pre-Compile [clock format [clock second ] -format %T] [expr [mem] /1024]M"
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set compile_final_drc_fix all
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set compile_automatic_clock_phase_inference relaxed
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set compile_enable_constant_propagation_with_no_boundary_opt true
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set compile_advanced_fix_multiple_port_nets true
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set compile_rewire_multiple_port_nets true
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set_fix_multiple_port_nets -all -buffer_constants [get_designs *]
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set_auto_disable_drc_nets -clock true -constant true -on_clock_network true
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#copied from original /script/vp_fp.03-05-2020_20.30.59.sdc, TODO: define accurate constraints and optimizations#
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# write_sdc output/rvh1.synth.elaborate.sdc
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# report_clock_tree -structure > rpt/clock_tree_structure.rpt
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#for dbg#
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#--------------------- Define clock gating -------------------------#
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set_clock_gating_style -sequential_cell latch -positive_edge_logic {integrated} -negative_edge_logic {integrated} \
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-control_point before -control_signal scan_enable \
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-minimum_bitwidth 4 -observation_point false \
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-max_fanout 16
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set_clock_latency 0 [all_clocks]
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set_clock_gate_latency -overwrite -stage 0 -fanout_latency {1-inf 0}
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set_clock_gate_latency -overwrite -stage 1 -fanout_latency {1-inf -0.05}
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set_clock_gate_latency -overwrite -stage 2 -fanout_latency {1-inf -0.1}
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set_clock_gate_latency -overwrite -stage 3 -fanout_latency {1-inf -0.15}
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set_clock_gate_latency -overwrite -stage 4 -fanout_latency {1-inf -0.2}
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set_clock_gate_latency -overwrite -stage 5 -fanout_latency {1-inf -0.25}
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set ALL_INPUTS [all_inputs]
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foreach_in_collection INPUTS $ALL_INPUTS {
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append_to_collection -unique INPUT_REG [ filter_collection [all_fanout -from $INPUTS -flat -endpoints_only] "full_name =~ */synch_toggle || full_name =~ */synch_preset || full_name =~ */synch_enable || full_name =~ */synch_clear || full_name =~ */next_state "]
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}
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set_clock_gating_objects -exclude [get_cells -of_object $INPUT_REG]
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#--------------------- Select compile strategy -------------------------#
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#--------------------- Synthesize and optimize the design ------------------------#
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# echo [get_object_name [get_lib_cells */* -filter dont_use==true]] > rpt/dont_use_list.rpt
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# check_design > rpt/check_design.precompile.rpt
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#for dbg#
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set_verification_top
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#set_dynamic_optimization true
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#run 2 times compile_ultra
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compile_ultra -gate_clock -retime -no_autoungroup -no_boundary_optimization
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compile_ultra -gate_clock -retime -no_autoungroup -no_boundary_optimization
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#compile_ultra (of DC Ultra) provides concurrent optimization of timing, area, power, and test for high performance designs#
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#it also provides advanced delay and arithmetic optimization, advanced timing analysis, automatic leakage power optimization, and register retiming#
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#--------------------- Analyze and debug the design/resolve design problems --------------------#
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analyze_datapath > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/datapath.compile.rpt
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report_resources > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/resources.compile.rpt
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write_file -hierarchy -format verilog -output ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/output/rvh1.synth.compile.v
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write_sdc ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/output/rvh1.synth.compile.sdc
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update_timing
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report_timing -nosplit > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/timing.compile.rpt
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report_area -nosplit -hier > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/area.hier.compile.rpt
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check_design > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/check_design.preopt.rpt
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optimize_netlist -area -no_boundary_optimization
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check_design > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/check_design.postopt.rpt
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define_name_rules preserve_struct_bus_rule -preserve_struct_ports
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define_name_rules ours_verilog_name_rule -allowed "a-z A-Z 0-9 _" \
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-check_internal_net_name \
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-case_insensitive
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change_names -rules preserve_struct_bus_rule -hierarchy -log_changes ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/struct_name_change.log
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change_names -rules ours_verilog_name_rule -hierarchy -log_changes ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/legalize_name_change.log
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write -format verilog -hierarchy -output ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/output/rvh1.synth.final.v
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write -format ddc -hierarchy -output ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/output/rvh1.synth.final.ddc
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write_sdc -nosplit ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/output/rvh1.synth.final.sdc
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report_clock_gating > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/clock_gating.rpt
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report_timing -tran -net -input -max_paths 500 -significant_digits 3 -nosplit > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/synth.timing.rpt
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report_timing -delay_type min -max_paths 500 -input_pins -nets -transition_time -capacitance -significant_digits 3 > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/synth.min_delay.rpt
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report_timing -delay_type max -max_paths 500 -input_pins -nets -transition_time -capacitance -significant_digits 3 > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/synth.max_delay.rpt
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report_constraint -all_violators -significant_digits 3 > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/synth.all_viol_constraints.rpt
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report_area -nosplit -hier > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/synth.area.hier.rpt
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report_resources -nosplit -hier > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/synth.resources.rpt
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report_timing_requirements > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/synth.mulcycle.rpt
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report_compile_options -nosplit > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/synth.compile_options.rpt
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#report_timing -tran -net -input -max_paths 1000 > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/timing.rpt
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report_clock_gating -nosplit -verbose -multi_stage > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/clock_gating.rpt
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report_clock_gating -gated -nosplit -verbose > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/clock_gating_gated.rpt
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report_clock_gating -ungated -nosplit -verbose > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/clock_ungating_gated.rpt
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report_power -nosplit > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/power.rpt
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report_qor > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/qor.rpt
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#report_area -hierarchy > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/area.rpt
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#report_constraint -all_violators -verbose -max_capacitance -max_transition > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/drc.rpt
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report_clocks > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/clock.rpt
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check_design -unmapped > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/check_design.rpt
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#check_timing -include {clock_no_period data_check_no_clock generated_clock generic} ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/check_timing.rpt
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report_dont_touch -nosplit -class cell > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/dont_touch.rpt
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report_threshold_voltage_group > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/threshold_voltage_group.rpt
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#--------------------- Save the design database ---------------------#
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write_file -format ddc -hierarchy -output ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/output/${DESIGN_NAME}.ddc
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#.ddc is the whole project, can be modified and checked#
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write_file -format verilog -hierarchy -output ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/output/${DESIGN_NAME}_netlist.v
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#netlist.v for P&R and sim#
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#write_sdf ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/output/${DESIGN_NAME}_sdf
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#recording the latency of std cells, also useful for post-sim#
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#write_parasitics -output ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/output/${DESIGN_NAME}_parasitics
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#Writes parasitics in SPEF format or as a Tcl script that contains set_load and set_resistance commands.#
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# write_sdc sdc_file_name
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#Writes out a script in Synopsys Design Constraints (SDC) format.#
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#This script contains commands that can be used with PrimeTime or with Design Compiler. SDC is also licensed by external vendors through the Tap-in program. SDC-formatted script files are read into PrimeTime or Design Compiler using the read_sdc command.#
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# write_floorplan -all ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/output/${DESIGN_NAME}_phys_cstr_file_name.tcl
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#writes a Tcl script file that contains floorplan information for the current or user-specified design. writes commands relative to the top of the design, regardless of the current instance.#
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#-------------------------------------------------------------------#
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echo "RUN ENDED AT [date]"
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