37 lines
830 B
Systemverilog
Executable File
37 lines
830 B
Systemverilog
Executable File
//===============================================
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//Name : STD_DFFRE
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//Author : cuiluping
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//Email : luping.cui@rivai-ic.com.cn
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//Date : 2019-08-24
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//Description : with reset ,with enable D flip flop
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//-----------------------------------------------
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//All Rights Reserved by rivai company
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//===============================================
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module std_dffre
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#(
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parameter WIDTH = 8
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)
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(
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input clk,
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input rstn,
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input en,
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input [WIDTH-1:0] d,
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output [WIDTH-1:0] q
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);
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logic [WIDTH-1:0] dff_q;
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always_ff @(posedge clk or negedge rstn) begin
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if(~rstn)begin
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dff_q <= {WIDTH{1'b0}};
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end
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else if(en)begin
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dff_q <= d;
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end
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end
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assign q = dff_q;
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endmodule
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