47 lines
745 B
Verilog
47 lines
745 B
Verilog
// Simple Dual-Port Block RAM with One Clock
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// reference: https://docs.xilinx.com/r/en-US/ug901-vivado-synthesis/Single-Port-Block-RAM-No-Change-Mode-Verilog
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// File: simple_dual_one_clock.v
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module simple_dual_one_clock
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#(
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parameter ADDR_BITS = 4,
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parameter DATA_BITS = 8
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// parameter RAM_LATENCY = 1,
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// parameter WE_SIZE = 1,
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)
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(clk,ena,enb,wea,addra,addrb,dia,dob);
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input clk,ena,enb,wea;
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input [ADDR_BITS-1:0] addra,addrb;
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input [DATA_BITS-1:0] dia;
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output [DATA_BITS-1:0] dob;
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reg [DATA_BITS-1:0] ram [(1'b1<<ADDR_BITS)-1:0];
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reg [DATA_BITS-1:0] doa,dob;
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always @(posedge clk) begin
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if (ena) begin
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if (wea)
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ram[addra] <= dia;
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end
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end
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always @(posedge clk) begin
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if (enb)
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dob <= ram[addrb];
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end
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endmodule |