143 lines
4.0 KiB
Systemverilog
143 lines
4.0 KiB
Systemverilog
module sa_local
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import rvh_noc_pkg::*;
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#(
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parameter INPUT_NUM = 4,
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parameter INPUT_NUM_IDX_W = INPUT_NUM > 1 ? $clog2(INPUT_NUM) : 1
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)
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(
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// input to allocate
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input logic [INPUT_NUM-1:0] vc_ctrl_head_vld_i,
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input flit_dec_t [INPUT_NUM-1:0] vc_ctrl_head_i,
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// output to global allocate
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output logic [OUTPUT_PORT_NUMBER-1:0] sa_local_vld_to_sa_global_o,
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output logic sa_local_vld_o,
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output logic [INPUT_NUM_IDX_W-1:0] sa_local_vc_id_o,
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output logic [INPUT_NUM-1:0] sa_local_vc_id_oh_o,
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`ifdef USE_QOS_VALUE
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output logic [QoS_Value_Width-1:0] sa_local_qos_value_o,
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`endif
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`ifdef VC_DATA_USE_DUAL_PORT_RAM
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output dpram_used_idx_t sa_local_dpram_idx_o,
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`endif
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// input pop flit ctrl fifo (comes from SA stage), use to update rr arbiter pointer
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input logic inport_read_enable_sa_stage_i,
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input logic clk,
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input logic rstn
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);
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genvar i,j;
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logic [INPUT_NUM-1:0] sa_local_grt_oh;
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logic [INPUT_NUM_IDX_W-1:0] sa_local_grt_idx;
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logic [INPUT_NUM-1:0] vc_ctrl_head_vld_join_arb; // for qos, if no qos, it is same as vc_ctrl_head_vld_i
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io_port_t [INPUT_NUM-1:0] vc_ctrl_head_i_look_ahead_routing;
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logic [INPUT_NUM-1:0][OUTPUT_PORT_NUMBER-1:0] vc_ctrl_head_i_look_ahead_routing_match;
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`ifdef USE_QOS_VALUE
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logic [QoS_Value_Width-1:0] vc_ctrl_head_i_qos_value_sel;
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`endif
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flit_dec_t vc_ctrl_head_sel;
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`ifdef USE_QOS_VALUE
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logic [INPUT_NUM-1:0][QoS_Value_Width-1:0] vc_ctrl_head_qos_value;
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generate
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for(i = 0; i < INPUT_NUM; i++) begin: gen_vc_ctrl_head_qos_value
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assign vc_ctrl_head_qos_value [i] = vc_ctrl_head_i[i].qos_value;
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end
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endgenerate
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priority_req_select
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#(
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.INPUT_NUM ( INPUT_NUM ),
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.INPUT_PRIORITY_W ( QoS_Value_Width )
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)
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sa_local_priority_req_select_u (
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.req_vld_i (vc_ctrl_head_vld_i ),
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.req_priority_i (vc_ctrl_head_qos_value ),
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.req_vld_o (vc_ctrl_head_vld_join_arb )
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);
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`else
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assign vc_ctrl_head_vld_join_arb = vc_ctrl_head_vld_i;
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`endif
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one_hot_rr_arb #(
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.N_INPUT (INPUT_NUM),
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.TIMEOUT_UPDATE_EN (1 ),
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.TIMEOUT_UPDATE_CYCLE (10)
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)
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sa_local_rr_arb_u
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(
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.req_i (vc_ctrl_head_vld_join_arb ),
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.update_i (inport_read_enable_sa_stage_i), // use global arbiter result to update: if win the global arbiter update local rr arbiter, or may be no fair
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.grt_o (sa_local_grt_oh ),
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.grt_idx_o (sa_local_grt_idx ),
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.rstn (rstn ),
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.clk (clk )
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);
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assign sa_local_vc_id_o = sa_local_grt_idx;
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assign sa_local_vc_id_oh_o = sa_local_grt_oh;
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`ifdef USE_QOS_VALUE
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assign sa_local_qos_value_o = vc_ctrl_head_sel.qos_value;
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`endif
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`ifdef VC_DATA_USE_DUAL_PORT_RAM
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assign sa_local_dpram_idx_o.dpram_idx = vc_ctrl_head_sel.dpram_used_idx.dpram_idx;
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assign sa_local_dpram_idx_o.per_vc_idx = vc_ctrl_head_sel.dpram_used_idx.per_vc_idx;
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`endif
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assign sa_local_vld_o = |vc_ctrl_head_vld_join_arb;
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generate
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for(i = 0; i < OUTPUT_PORT_NUMBER; i++) begin
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assign sa_local_vld_to_sa_global_o[i] = vc_ctrl_head_vld_join_arb[sa_local_grt_idx] &
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vc_ctrl_head_i_look_ahead_routing_match[sa_local_grt_idx][i];
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end
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endgenerate
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generate
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for(i = 0; i < INPUT_NUM; i++) begin
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assign vc_ctrl_head_i_look_ahead_routing[i] = vc_ctrl_head_i[i].look_ahead_routing;
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end
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endgenerate
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generate
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for(i = 0; i < INPUT_NUM; i++) begin: gen_vc_ctrl_head_i_look_ahead_routing_match_i
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for(j = 0; j < OUTPUT_PORT_NUMBER; j++) begin: gen_vc_ctrl_head_i_look_ahead_routing_match_j
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assign vc_ctrl_head_i_look_ahead_routing_match[i][j] = vc_ctrl_head_i_look_ahead_routing[i] == j[$bits(io_port_t)-1:0];
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end
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end
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endgenerate
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onehot_mux
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#(
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.SOURCE_COUNT(INPUT_NUM ),
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.DATA_WIDTH ($bits(flit_dec_t))
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)
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onehot_mux_qos_value_sel_u (
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.sel_i (sa_local_grt_oh ),
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.data_i (vc_ctrl_head_i ),
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.data_o (vc_ctrl_head_sel)
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);
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endmodule
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