50 lines
1.1 KiB
Systemverilog
Executable File
50 lines
1.1 KiB
Systemverilog
Executable File
`ifndef __ONE_COUNTER_SV__
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`define __ONE_COUNTER_SV__
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module one_counter
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#(
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parameter int unsigned DATA_WIDTH = 8,
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localparam int unsigned CNT_WIDTH = $clog2(DATA_WIDTH) + 1
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)
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(
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input logic[DATA_WIDTH-1:0] data_i,
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output logic[CNT_WIDTH-1:0] cnt_o
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);
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localparam int unsigned PADDED_DATA_WIDTH = 1 << $clog2(DATA_WIDTH);
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logic [PADDED_DATA_WIDTH-1:0] padded_data;
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always_comb begin
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padded_data = {PADDED_DATA_WIDTH{1'b0}};
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padded_data[DATA_WIDTH-1:0] = data_i;
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end
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if(DATA_WIDTH == 1) begin
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assign cnt_o = data_i;
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end else begin
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logic [CNT_WIDTH-2:0] res_left,res_right;
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assign cnt_o = res_left + res_right;
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one_counter #(
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.DATA_WIDTH(PADDED_DATA_WIDTH/2)
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) one_counter_left_u (
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.data_i(padded_data[PADDED_DATA_WIDTH-1:PADDED_DATA_WIDTH/2]),
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.cnt_o(res_left)
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);
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one_counter #(
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.DATA_WIDTH(PADDED_DATA_WIDTH/2)
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) one_counter_right_u (
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.data_i(padded_data[PADDED_DATA_WIDTH/2-1:0]),
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.cnt_o(res_right)
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);
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end
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endmodule : one_counter
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`endif |