Add Ethernet MAC model
This commit is contained in:
Alex Forencich
@@ -28,5 +28,6 @@ from .gmii import GmiiFrame, GmiiSource, GmiiSink, GmiiPhy
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from .mii import MiiSource, MiiSink, MiiPhy
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from .rgmii import RgmiiSource, RgmiiSink, RgmiiPhy
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from .xgmii import XgmiiFrame, XgmiiSource, XgmiiSink
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from .eth_mac import EthMacFrame, EthMacTx, EthMacRx, EthMac
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from .ptp import PtpClock, PtpClockSimTime
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533
cocotbext/eth/eth_mac.py
Normal file
533
cocotbext/eth/eth_mac.py
Normal file
@@ -0,0 +1,533 @@
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"""
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Copyright (c) 2021 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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"""
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import logging
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import struct
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import zlib
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import cocotb
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from cocotb.queue import Queue, QueueFull
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from cocotb.triggers import RisingEdge, Timer, First, Event
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from cocotb.utils import get_sim_time
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from cocotbext.axi.stream import define_stream
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from .version import __version__
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from .reset import Reset
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AxiStreamBus, AxiStreamTransaction, AxiStreamSource, AxiStreamSink, AxiStreamMonitor = define_stream("AxiStream",
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signals=["tvalid", "tdata", "tkeep", "tlast", "tuser"],
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optional_signals=["tready"]
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)
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class EthMacFrame:
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def __init__(self, data=None, tx_complete=None):
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self.data = bytearray()
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self.sim_time_start = None
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self.sim_time_sfd = None
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self.sim_time_end = None
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self.ptp_timestamp = None
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self.tx_complete = None
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if type(data) is EthMacFrame:
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self.data = bytearray(data.data)
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self.sim_time_start = data.sim_time_start
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self.sim_time_sfd = data.sim_time_sfd
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self.sim_time_end = data.sim_time_end
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self.ptp_timestamp = data.ptp_timestamp
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self.tx_complete = data.tx_complete
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else:
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self.data = bytearray(data)
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if tx_complete is not None:
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self.tx_complete = tx_complete
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@classmethod
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def from_payload(cls, payload, min_len=60, tx_complete=None):
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payload = bytearray(payload)
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if len(payload) < min_len:
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payload.extend(bytearray(min_len-len(payload)))
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payload.extend(struct.pack('<L', zlib.crc32(payload)))
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return cls(payload, tx_complete=tx_complete)
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@classmethod
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def from_raw_payload(cls, payload, tx_complete=None):
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return cls(payload, tx_complete=tx_complete)
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def get_payload(self, strip_fcs=True):
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if strip_fcs:
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return self.data[:-4]
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else:
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return self.data
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def get_fcs(self):
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return self.data[-4:]
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def check_fcs(self):
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return self.get_fcs() == struct.pack('<L', zlib.crc32(self.get_payload(strip_fcs=True)))
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def handle_tx_complete(self):
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if isinstance(self.tx_complete, Event):
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self.tx_complete.set(self)
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elif callable(self.tx_complete):
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self.tx_complete(self)
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def __eq__(self, other):
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if type(other) is EthMacFrame:
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return self.data == other.data
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def __repr__(self):
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return (
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f"{type(self).__name__}(data={self.data!r}, "
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f"sim_time_start={self.sim_time_start!r}, "
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f"sim_time_sfd={self.sim_time_sfd!r}, "
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f"sim_time_end={self.sim_time_end!r}, "
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f"ptp_timestamp={self.ptp_timestamp!r})"
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)
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def __len__(self):
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return len(self.data)
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def __iter__(self):
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return self.data.__iter__()
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def __bytes__(self):
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return bytes(self.data)
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class EthMacTx(Reset):
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def __init__(self, bus, clock, reset=None, ptp_time=None, ptp_ts=None, ptp_ts_valid=None,
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reset_active_level=True, ifg=12, speed=1000e6, *args, **kwargs):
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self.bus = bus
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self.clock = clock
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self.reset = reset
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self.ptp_time = ptp_time
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self.ptp_ts = ptp_ts
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self.ptp_ts_valid = ptp_ts_valid
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self.ifg = ifg
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self.speed = speed
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self.log = logging.getLogger(f"cocotb.{bus._entity._name}.{bus._name}")
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self.log.info("Ethernet MAC TX model")
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self.log.info("cocotbext-eth version %s", __version__)
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self.log.info("Copyright (c) 2020 Alex Forencich")
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self.log.info("https://github.com/alexforencich/cocotbext-eth")
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super().__init__(*args, **kwargs)
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self.stream = AxiStreamSink(bus, clock, reset, reset_active_level=reset_active_level)
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self.stream.queue_occupancy_limit = 4
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self.active = False
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self.queue = Queue()
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self.active_event = Event()
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self.ts_queue = Queue()
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self.queue_occupancy_bytes = 0
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self.queue_occupancy_frames = 0
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self.time_scale = cocotb.utils.get_sim_steps(1, 'sec')
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self.width = len(self.bus.tdata)
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self.byte_lanes = 1
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if hasattr(self.bus, "tkeep"):
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self.byte_lanes = len(self.bus.tkeep)
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self.byte_size = self.width // self.byte_lanes
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self.byte_mask = 2**self.byte_size-1
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self.log.info("Ethernet MAC TX model configuration")
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self.log.info(" Byte size: %d bits", self.byte_size)
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self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes)
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if hasattr(self.bus, "tkeep"):
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self.log.info(" tkeep width: %d bits", len(self.bus.tkeep))
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else:
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self.log.info(" tkeep: not present")
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if hasattr(self.bus, "tuser"):
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self.log.info(" tuser width: %d bits", len(self.bus.tuser))
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else:
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self.log.info(" tuser: not present")
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if self.bus.tready is None:
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raise ValueError("tready is required")
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if self.byte_size != 8:
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raise ValueError("Byte size must be 8")
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if self.byte_lanes * self.byte_size != self.width:
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raise ValueError(f"Bus does not evenly divide into byte lanes "
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f"({self.byte_lanes} * {self.byte_size} != {self.width})")
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if self.ptp_ts:
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self.ptp_ts.setimmediatevalue(0)
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if self.ptp_ts_valid:
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self.ptp_ts_valid.setimmediatevalue(0)
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self._run_cr = None
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self._run_ts_cr = None
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self._init_reset(reset, reset_active_level)
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def _recv(self, frame):
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if self.queue.empty():
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self.active_event.clear()
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self.queue_occupancy_bytes -= len(frame)
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self.queue_occupancy_frames -= 1
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return frame
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async def recv(self):
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frame = await self.queue.get()
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return self._recv(frame)
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def recv_nowait(self):
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frame = self.queue.get_nowait()
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return self._recv(frame)
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def count(self):
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return self.queue.qsize()
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def empty(self):
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return self.queue.empty()
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def idle(self):
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return not self.active
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def clear(self):
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while not self.queue.empty():
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self.queue.get_nowait()
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self.active_event.clear()
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self.queue_occupancy_bytes = 0
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self.queue_occupancy_frames = 0
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async def wait(self, timeout=0, timeout_unit=None):
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if not self.empty():
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return
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if timeout:
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await First(self.active_event.wait(), Timer(timeout, timeout_unit))
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else:
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await self.active_event.wait()
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def _handle_reset(self, state):
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if state:
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self.log.info("Reset asserted")
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if self._run_cr is not None:
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self._run_cr.kill()
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self._run_cr = None
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if self._run_ts_cr is not None:
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self._run_ts_cr.kill()
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self._run_ts_cr = None
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if self.ptp_ts_valid:
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self.ptp_ts_valid <= 0
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self.active = False
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while not self.ts_queue.empty():
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self.ts_queue.get_nowait()
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else:
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self.log.info("Reset de-asserted")
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if self._run_cr is None:
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self._run_cr = cocotb.fork(self._run())
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if self._run_ts_cr is None and self.ptp_ts:
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self._run_ts_cr = cocotb.fork(self._run_ts())
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async def _run(self):
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frame = None
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self.active = False
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while True:
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# wait for data
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cycle = await self.stream.recv()
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frame = EthMacFrame(bytearray())
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frame.sim_time_start = get_sim_time()
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# wait for preamble time
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await Timer(self.time_scale*8*8//self.speed, 'step')
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frame.sim_time_sfd = get_sim_time()
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if self.ptp_time:
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frame.ptp_timestamp = self.ptp_time.value.integer
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self.ts_queue.put_nowait(frame.ptp_timestamp)
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# process frame data
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while True:
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byte_count = 0
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for offset in range(self.byte_lanes):
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if not hasattr(self.bus, "tkeep") or (cycle.tkeep.integer >> offset) & 1:
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frame.data.append((cycle.tdata.integer >> (offset * self.byte_size)) & self.byte_mask)
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byte_count += 1
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# wait for serialization time
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await Timer(self.time_scale*byte_count*8//self.speed, 'step')
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if cycle.tlast.integer:
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frame.sim_time_end = get_sim_time()
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self.log.info("RX frame: %s", frame)
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self.queue_occupancy_bytes += len(frame)
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self.queue_occupancy_frames += 1
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await self.queue.put(frame)
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self.active_event.set()
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frame = None
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break
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# get next cycle
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# TODO improve underflow handling
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assert not self.stream.empty(), "underflow"
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cycle = await self.stream.recv()
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# wait for IFG
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await Timer(self.time_scale*self.ifg*8//self.speed, 'step')
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async def _run_ts(self):
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while True:
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await RisingEdge(self.clock)
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self.ptp_ts_valid <= 0
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if not self.ts_queue.empty():
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ts = self.ts_queue.get_nowait()
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self.ptp_ts <= ts
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self.ptp_ts_valid <= 1
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class EthMacRx(Reset):
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def __init__(self, bus, clock, reset=None, ptp_time=None,
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reset_active_level=True, ifg=12, speed=1000e6, *args, **kwargs):
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self.bus = bus
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self.clock = clock
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self.reset = reset
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self.ptp_time = ptp_time
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self.ifg = ifg
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self.speed = speed
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self.log = logging.getLogger(f"cocotb.{bus._entity._name}.{bus._name}")
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self.log.info("Ethernet MAC RX model")
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self.log.info("cocotbext-eth version %s", __version__)
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self.log.info("Copyright (c) 2020 Alex Forencich")
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self.log.info("https://github.com/alexforencich/cocotbext-eth")
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super().__init__(*args, **kwargs)
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self.stream = AxiStreamSource(bus, clock, reset, reset_active_level=reset_active_level)
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self.stream.queue_occupancy_limit = 4
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self.active = False
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self.queue = Queue()
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self.dequeue_event = Event()
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self.current_frame = None
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self.idle_event = Event()
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self.idle_event.set()
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self.queue_occupancy_bytes = 0
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self.queue_occupancy_frames = 0
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self.queue_occupancy_limit_bytes = -1
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self.queue_occupancy_limit_frames = -1
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self.time_scale = cocotb.utils.get_sim_steps(1, 'sec')
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self.width = len(self.bus.tdata)
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self.byte_lanes = 1
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if hasattr(self.bus, "tkeep"):
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self.byte_lanes = len(self.bus.tkeep)
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self.byte_size = self.width // self.byte_lanes
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self.byte_mask = 2**self.byte_size-1
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self.log.info("Ethernet MAC RX model configuration")
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self.log.info(" Byte size: %d bits", self.byte_size)
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self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes)
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if hasattr(self.bus, "tkeep"):
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self.log.info(" tkeep width: %d bits", len(self.bus.tkeep))
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else:
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self.log.info(" tkeep: not present")
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if hasattr(self.bus, "tuser"):
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self.log.info(" tuser width: %d bits", len(self.bus.tuser))
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else:
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self.log.info(" tuser: not present")
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if self.byte_size != 8:
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raise ValueError("Byte size must be 8")
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if self.byte_lanes * self.byte_size != self.width:
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raise ValueError(f"Bus does not evenly divide into byte lanes "
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f"({self.byte_lanes} * {self.byte_size} != {self.width})")
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self._run_cr = None
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self._init_reset(reset, reset_active_level)
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async def send(self, frame):
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while self.full():
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self.dequeue_event.clear()
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await self.dequeue_event.wait()
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frame = EthMacFrame(frame)
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await self.queue.put(frame)
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self.idle_event.clear()
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self.queue_occupancy_bytes += len(frame)
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self.queue_occupancy_frames += 1
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def send_nowait(self, frame):
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if self.full():
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raise QueueFull()
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frame = EthMacFrame(frame)
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self.queue.put_nowait(frame)
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self.idle_event.clear()
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self.queue_occupancy_bytes += len(frame)
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self.queue_occupancy_frames += 1
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def count(self):
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return self.queue.qsize()
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def empty(self):
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return self.queue.empty()
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def full(self):
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if self.queue_occupancy_limit_bytes > 0 and self.queue_occupancy_bytes > self.queue_occupancy_limit_bytes:
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return True
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elif self.queue_occupancy_limit_frames > 0 and self.queue_occupancy_frames > self.queue_occupancy_limit_frames:
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return True
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else:
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return False
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def idle(self):
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return self.empty() and not self.active
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def clear(self):
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while not self.queue.empty():
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frame = self.queue.get_nowait()
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frame.sim_time_end = None
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frame.handle_tx_complete()
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self.dequeue_event.set()
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self.idle_event.set()
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self.queue_occupancy_bytes = 0
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self.queue_occupancy_frames = 0
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async def wait(self):
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await self.idle_event.wait()
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def _handle_reset(self, state):
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if state:
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self.log.info("Reset asserted")
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if self._run_cr is not None:
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self._run_cr.kill()
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self._run_cr = None
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self.active = False
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if self.current_frame:
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self.log.warning("Flushed transmit frame during reset: %s", self.current_frame)
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self.current_frame.handle_tx_complete()
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self.current_frame = None
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if self.queue.empty():
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self.idle_event.set()
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else:
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self.log.info("Reset de-asserted")
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if self._run_cr is None:
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self._run_cr = cocotb.fork(self._run())
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async def _run(self):
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frame = None
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tuser = 0
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self.active = False
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while True:
|
||||
# wait for data
|
||||
frame = await self.queue.get()
|
||||
tuser = 0
|
||||
self.dequeue_event.set()
|
||||
self.queue_occupancy_bytes -= len(frame)
|
||||
self.queue_occupancy_frames -= 1
|
||||
self.current_frame = frame
|
||||
frame.sim_time_start = get_sim_time()
|
||||
frame.sim_time_sfd = None
|
||||
frame.sim_time_end = None
|
||||
self.log.info("TX frame: %s", frame)
|
||||
|
||||
# wait for preamble time
|
||||
await Timer(self.time_scale*8*8//self.speed, 'step')
|
||||
|
||||
frame.sim_time_sfd = get_sim_time()
|
||||
|
||||
if self.ptp_time:
|
||||
frame.ptp_timestamp = self.ptp_time.value.integer
|
||||
tuser |= frame.ptp_timestamp << 1
|
||||
|
||||
# process frame data
|
||||
while frame is not None:
|
||||
byte_count = 0
|
||||
|
||||
cycle = AxiStreamTransaction()
|
||||
|
||||
cycle.tdata = 0
|
||||
cycle.tkeep = 0
|
||||
cycle.tlast = 0
|
||||
cycle.tuser = tuser
|
||||
|
||||
for offset in range(self.byte_lanes):
|
||||
cycle.tdata |= (frame.data.pop(0) & self.byte_mask) << (offset * self.byte_size)
|
||||
cycle.tkeep |= 1 << offset
|
||||
byte_count += 1
|
||||
|
||||
if len(frame.data) == 0:
|
||||
cycle.tlast = 1
|
||||
frame.sim_time_end = get_sim_time()
|
||||
frame.handle_tx_complete()
|
||||
frame = None
|
||||
self.current_frame = None
|
||||
break
|
||||
|
||||
await self.stream.send(cycle)
|
||||
|
||||
# wait for serialization time
|
||||
await Timer(self.time_scale*byte_count*8//self.speed, 'step')
|
||||
|
||||
# wait for IFG
|
||||
await Timer(self.time_scale*self.ifg*8//self.speed, 'step')
|
||||
|
||||
|
||||
class EthMac:
|
||||
def __init__(self, tx_bus=None, tx_clk=None, tx_rst=None, tx_ptp_time=None, tx_ptp_ts=None, tx_ptp_ts_valid=None,
|
||||
rx_bus=None, rx_clk=None, rx_rst=None, rx_ptp_time=None,
|
||||
reset_active_level=True, ifg=12, speed=1000e6, *args, **kwargs):
|
||||
|
||||
super().__init__(*args, **kwargs)
|
||||
|
||||
self.tx = EthMacTx(tx_bus, tx_clk, tx_rst, tx_ptp_time, tx_ptp_ts, tx_ptp_ts_valid,
|
||||
reset_active_level=reset_active_level, ifg=ifg, speed=speed)
|
||||
self.rx = EthMacRx(rx_bus, rx_clk, rx_rst, rx_ptp_time,
|
||||
reset_active_level=reset_active_level, ifg=ifg, speed=speed)
|
||||
61
tests/eth_mac/Makefile
Normal file
61
tests/eth_mac/Makefile
Normal file
@@ -0,0 +1,61 @@
|
||||
# Copyright (c) 2021 Alex Forencich
|
||||
#
|
||||
# Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
# of this software and associated documentation files (the "Software"), to deal
|
||||
# in the Software without restriction, including without limitation the rights
|
||||
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
# copies of the Software, and to permit persons to whom the Software is
|
||||
# furnished to do so, subject to the following conditions:
|
||||
#
|
||||
# The above copyright notice and this permission notice shall be included in
|
||||
# all copies or substantial portions of the Software.
|
||||
#
|
||||
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
# THE SOFTWARE.
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= icarus
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ns
|
||||
|
||||
DUT = test_eth_mac
|
||||
TOPLEVEL = $(DUT)
|
||||
MODULE = $(DUT)
|
||||
VERILOG_SOURCES += $(DUT).v
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
VERILOG_SOURCES += iverilog_dump.v
|
||||
COMPILE_ARGS += -s iverilog_dump
|
||||
endif
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
|
||||
iverilog_dump.v:
|
||||
echo 'module iverilog_dump();' > $@
|
||||
echo 'initial begin' >> $@
|
||||
echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@
|
||||
echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@
|
||||
echo 'end' >> $@
|
||||
echo 'endmodule' >> $@
|
||||
|
||||
clean::
|
||||
@rm -rf iverilog_dump.v
|
||||
@rm -rf dump.fst $(TOPLEVEL).fst
|
||||
197
tests/eth_mac/test_eth_mac.py
Normal file
197
tests/eth_mac/test_eth_mac.py
Normal file
@@ -0,0 +1,197 @@
|
||||
#!/usr/bin/env python
|
||||
"""
|
||||
|
||||
Copyright (c) 2021 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
|
||||
import cocotb_test.simulator
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.eth import EthMacFrame, EthMac, PtpClockSimTime
|
||||
from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink
|
||||
|
||||
|
||||
class TB:
|
||||
def __init__(self, dut, speed=10e9):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.fork(Clock(dut.tx_clk, 6.4, units="ns").start())
|
||||
cocotb.fork(Clock(dut.rx_clk, 6.4, units="ns").start())
|
||||
|
||||
self.mac = EthMac(
|
||||
tx_clk=dut.tx_clk,
|
||||
tx_rst=dut.tx_rst,
|
||||
tx_bus=AxiStreamBus.from_prefix(dut, "tx_axis"),
|
||||
tx_ptp_time=dut.tx_ptp_time,
|
||||
tx_ptp_ts=dut.tx_ptp_ts,
|
||||
tx_ptp_ts_valid=dut.tx_ptp_ts_valid,
|
||||
rx_clk=dut.rx_clk,
|
||||
rx_rst=dut.rx_rst,
|
||||
rx_bus=AxiStreamBus.from_prefix(dut, "rx_axis"),
|
||||
rx_ptp_time=dut.rx_ptp_time,
|
||||
ifg=12, speed=speed
|
||||
)
|
||||
|
||||
self.tx_ptp = PtpClockSimTime(
|
||||
ts_96=dut.tx_ptp_time,
|
||||
clock=dut.tx_clk
|
||||
)
|
||||
|
||||
self.rx_ptp = PtpClockSimTime(
|
||||
ts_96=dut.rx_ptp_time,
|
||||
clock=dut.rx_clk
|
||||
)
|
||||
|
||||
self.source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "tx_axis"), dut.tx_clk, dut.tx_rst)
|
||||
self.sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "rx_axis"), dut.rx_clk, dut.rx_rst)
|
||||
|
||||
async def reset(self):
|
||||
self.dut.tx_rst.setimmediatevalue(0)
|
||||
self.dut.rx_rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.tx_clk)
|
||||
await RisingEdge(self.dut.tx_clk)
|
||||
self.dut.tx_rst <= 1
|
||||
self.dut.rx_rst <= 1
|
||||
await RisingEdge(self.dut.tx_clk)
|
||||
await RisingEdge(self.dut.tx_clk)
|
||||
self.dut.tx_rst <= 0
|
||||
self.dut.rx_rst <= 0
|
||||
await RisingEdge(self.dut.tx_clk)
|
||||
await RisingEdge(self.dut.tx_clk)
|
||||
|
||||
|
||||
async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, speed=10e9):
|
||||
|
||||
tb = TB(dut, speed)
|
||||
|
||||
tb.mac.tx.ifg = ifg
|
||||
tb.mac.rx.ifg = ifg
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_frames = [payload_data(x) for x in payload_lengths()]
|
||||
|
||||
for test_data in test_frames:
|
||||
test_frame = EthMacFrame.from_payload(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for test_data in test_frames:
|
||||
rx_frame = await tb.mac.tx.recv()
|
||||
|
||||
assert rx_frame.get_payload() == test_data
|
||||
assert rx_frame.check_fcs()
|
||||
|
||||
assert tb.mac.tx.empty()
|
||||
|
||||
await RisingEdge(dut.tx_clk)
|
||||
await RisingEdge(dut.tx_clk)
|
||||
|
||||
|
||||
async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, speed=10e9):
|
||||
|
||||
tb = TB(dut, speed)
|
||||
|
||||
tb.mac.tx.ifg = ifg
|
||||
tb.mac.rx.ifg = ifg
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_frames = [payload_data(x) for x in payload_lengths()]
|
||||
|
||||
for test_data in test_frames:
|
||||
test_frame = EthMacFrame.from_payload(test_data)
|
||||
await tb.mac.rx.send(test_frame)
|
||||
|
||||
for test_data in test_frames:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
check_frame = EthMacFrame(rx_frame.tdata)
|
||||
|
||||
assert check_frame.get_payload() == test_data
|
||||
assert check_frame.check_fcs()
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.rx_clk)
|
||||
await RisingEdge(dut.rx_clk)
|
||||
|
||||
|
||||
def size_list():
|
||||
return list(range(60, 128)) + [512, 1514, 9214] + [60]*10
|
||||
|
||||
|
||||
def incrementing_payload(length):
|
||||
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
|
||||
|
||||
if cocotb.SIM_NAME:
|
||||
|
||||
for test in [run_test_tx, run_test_rx]:
|
||||
|
||||
factory = TestFactory(test)
|
||||
factory.add_option("payload_lengths", [size_list])
|
||||
factory.add_option("payload_data", [incrementing_payload])
|
||||
factory.add_option("speed", [10e9, 1e9])
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.dirname(__file__)
|
||||
|
||||
|
||||
def test_eth_mac(request):
|
||||
dut = "test_eth_mac"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = dut
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{dut}.v"),
|
||||
]
|
||||
|
||||
parameters = {}
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
56
tests/eth_mac/test_eth_mac.v
Normal file
56
tests/eth_mac/test_eth_mac.v
Normal file
@@ -0,0 +1,56 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2021 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
* Ethernet MAC model test
|
||||
*/
|
||||
module test_eth_mac
|
||||
(
|
||||
inout wire tx_clk,
|
||||
inout wire tx_rst,
|
||||
inout wire [63:0] tx_axis_tdata,
|
||||
inout wire [7:0] tx_axis_tkeep,
|
||||
inout wire tx_axis_tlast,
|
||||
inout wire tx_axis_tuser,
|
||||
inout wire tx_axis_tvalid,
|
||||
inout wire tx_axis_tready,
|
||||
inout wire [95:0] tx_ptp_time,
|
||||
inout wire [95:0] tx_ptp_ts,
|
||||
inout wire tx_ptp_ts_valid,
|
||||
|
||||
inout wire rx_clk,
|
||||
inout wire rx_rst,
|
||||
inout wire [63:0] rx_axis_tdata,
|
||||
inout wire [7:0] rx_axis_tkeep,
|
||||
inout wire rx_axis_tlast,
|
||||
inout wire [96:0] rx_axis_tuser,
|
||||
inout wire rx_axis_tvalid,
|
||||
inout wire [95:0] rx_ptp_time
|
||||
);
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user