third-party/cocotbext-eth
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Cache clock edge event objects

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This commit is contained in:
Alex Forencich
2021-12-03 19:06:43 -08:00
parent 3325568406
commit 2af7852006
12 changed files with 68 additions and 41 deletions
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4
cocotbext/eth/eth_mac.py
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@@ -322,8 +322,10 @@ class EthMacTx(Reset):
await Timer(self.time_scale*self.ifg*8//self.speed, 'step') await Timer(self.time_scale*self.ifg*8//self.speed, 'step')
async def _run_ts(self): async def _run_ts(self):
clock_edge_event = RisingEdge(self.clock)
while True: while True:
await RisingEdge(self.clock) await clock_edge_event
self.ptp_ts_valid.value = 0 self.ptp_ts_valid.value = 0
if not self.ts_queue.empty(): if not self.ts_queue.empty():

8
cocotbext/eth/gmii.py
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@@ -264,8 +264,10 @@ class GmiiSource(Reset):
ifg_cnt = 0 ifg_cnt = 0
self.active = False self.active = False
clock_edge_event = RisingEdge(self.clock)
while True: while True:
await RisingEdge(self.clock) await clock_edge_event
if self.enable is None or self.enable.value: if self.enable is None or self.enable.value:
if ifg_cnt > 0: if ifg_cnt > 0:
@@ -428,8 +430,10 @@ class GmiiSink(Reset):
frame = None frame = None
self.active = False self.active = False
clock_edge_event = RisingEdge(self.clock)
while True: while True:
await RisingEdge(self.clock) await clock_edge_event
if self.enable is None or self.enable.value: if self.enable is None or self.enable.value:
d_val = self.data.value.integer d_val = self.data.value.integer

8
cocotbext/eth/mii.py
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@@ -165,8 +165,10 @@ class MiiSource(Reset):
ifg_cnt = 0 ifg_cnt = 0
self.active = False self.active = False
clock_edge_event = RisingEdge(self.clock)
while True: while True:
await RisingEdge(self.clock) await clock_edge_event
if self.enable is None or self.enable.value: if self.enable is None or self.enable.value:
if ifg_cnt > 0: if ifg_cnt > 0:
@@ -319,8 +321,10 @@ class MiiSink(Reset):
frame = None frame = None
self.active = False self.active = False
clock_edge_event = RisingEdge(self.clock)
while True: while True:
await RisingEdge(self.clock) await clock_edge_event
if self.enable is None or self.enable.value: if self.enable is None or self.enable.value:
d_val = self.data.value.integer d_val = self.data.value.integer

8
cocotbext/eth/ptp.py
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@@ -208,8 +208,10 @@ class PtpClock(Reset):
self._run_cr = cocotb.fork(self._run()) self._run_cr = cocotb.fork(self._run())
async def _run(self): async def _run(self):
clock_edge_event = RisingEdge(self.clock)
while True: while True:
await RisingEdge(self.clock) await clock_edge_event
if self.ts_step is not None: if self.ts_step is not None:
self.ts_step.value = self.ts_updated self.ts_step.value = self.ts_updated
@@ -309,8 +311,10 @@ class PtpClockSimTime:
return self.get_ts_64()*1e-9 return self.get_ts_64()*1e-9
async def _run(self): async def _run(self):
clock_edge_event = RisingEdge(self.clock)
while True: while True:
await RisingEdge(self.clock) await clock_edge_event
self.ts_64_fns, self.ts_64_ns = math.modf(get_sim_time('ns')) self.ts_64_fns, self.ts_64_ns = math.modf(get_sim_time('ns'))

38
cocotbext/eth/rgmii.py
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@@ -166,8 +166,11 @@ class RgmiiSource(Reset):
er = 0 er = 0
en = 0 en = 0
clock_rising_edge_event = RisingEdge(self.clock)
clock_falling_edge_event = FallingEdge(self.clock)
while True: while True:
await RisingEdge(self.clock) await clock_rising_edge_event
# send high nibble after rising edge, leading in to falling edge # send high nibble after rising edge, leading in to falling edge
self.data.value = d >> 4 self.data.value = d >> 4
@@ -232,11 +235,11 @@ class RgmiiSource(Reset):
self.active = False self.active = False
self.idle_event.set() self.idle_event.set()
await FallingEdge(self.clock) await clock_falling_edge_event
# send low nibble after falling edge, leading in to rising edge # send low nibble after falling edge, leading in to rising edge
self.data.value = d & 0x0F self.data.value = d & 0x0F
self.ctrl.value = en self.ctrl.value = en
class RgmiiSink(Reset): class RgmiiSink(Reset):
@@ -339,21 +342,24 @@ class RgmiiSink(Reset):
dv_val = 0 dv_val = 0
er_val = 0 er_val = 0
clock_rising_edge_event = RisingEdge(self.clock)
clock_falling_edge_event = FallingEdge(self.clock)
while True: while True:
await RisingEdge(self.clock) await clock_rising_edge_event
# capture low nibble on rising edge
d_val = self.data.value.integer
dv_val = self.ctrl.value.integer
await FallingEdge(self.clock)
# capture high nibble on falling edge
d_val |= self.data.value.integer << 4
er_val = dv_val ^ self.ctrl.value.integer
if self.enable is None or self.enable.value: if self.enable is None or self.enable.value:
# capture low nibble on rising edge
d_val = self.data.value.integer
dv_val = self.ctrl.value.integer
await clock_falling_edge_event
# capture high nibble on falling edge
d_val |= self.data.value.integer << 4
er_val = dv_val ^ self.ctrl.value.integer
if frame is None: if frame is None:
if dv_val: if dv_val:
# start of frame # start of frame

8
cocotbext/eth/xgmii.py
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@@ -272,8 +272,10 @@ class XgmiiSource(Reset):
deficit_idle_cnt = 0 deficit_idle_cnt = 0
self.active = False self.active = False
clock_edge_event = RisingEdge(self.clock)
while True: while True:
await RisingEdge(self.clock) await clock_edge_event
if self.enable is None or self.enable.value: if self.enable is None or self.enable.value:
if ifg_cnt + deficit_idle_cnt > self.byte_lanes-1 or (not self.enable_dic and ifg_cnt > 4): if ifg_cnt + deficit_idle_cnt > self.byte_lanes-1 or (not self.enable_dic and ifg_cnt > 4):
@@ -456,8 +458,10 @@ class XgmiiSink(Reset):
frame = None frame = None
self.active = False self.active = False
clock_edge_event = RisingEdge(self.clock)
while True: while True:
await RisingEdge(self.clock) await clock_edge_event
if self.enable is None or self.enable.value: if self.enable is None or self.enable.value:
for offset in range(self.byte_lanes): for offset in range(self.byte_lanes):

4
tests/gmii/test_gmii.py
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@@ -82,9 +82,11 @@ class TB:
self.set_enable_generator(None) self.set_enable_generator(None)
async def _run_enable(self): async def _run_enable(self):
clock_edge_event = RisingEdge(self.dut.clk)
for val in self._enable_generator: for val in self._enable_generator:
self.dut.gmii_clk_en <= val self.dut.gmii_clk_en <= val
await RisingEdge(self.dut.clk) await clock_edge_event
async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12, enable_gen=None, mii_sel=False): async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12, enable_gen=None, mii_sel=False):

4
tests/mii/test_mii.py
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@@ -81,9 +81,11 @@ class TB:
self.set_enable_generator(None) self.set_enable_generator(None)
async def _run_enable(self): async def _run_enable(self):
clock_edge_event = RisingEdge(self.dut.clk)
for val in self._enable_generator: for val in self._enable_generator:
self.dut.mii_clk_en <= val self.dut.mii_clk_en <= val
await RisingEdge(self.dut.clk) await clock_edge_event
async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12, enable_gen=None): async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12, enable_gen=None):

14
tests/ptp_clock/test_ptp_clock.py
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@@ -30,7 +30,7 @@ import cocotb_test.simulator
import cocotb import cocotb
from cocotb.clock import Clock from cocotb.clock import Clock
from cocotb.triggers import RisingEdge from cocotb.triggers import RisingEdge, ClockCycles
from cocotb.utils import get_sim_time from cocotb.utils import get_sim_time
from cocotbext.eth import PtpClock from cocotbext.eth import PtpClock
@@ -79,8 +79,7 @@ async def run_default_rate(dut):
start_ts_96 = (dut.ts_96.value.integer >> 48) + ((dut.ts_96.value.integer & 0xffffffffffff)/2**16*1e-9) start_ts_96 = (dut.ts_96.value.integer >> 48) + ((dut.ts_96.value.integer & 0xffffffffffff)/2**16*1e-9)
start_ts_64 = dut.ts_64.value.integer/2**16*1e-9 start_ts_64 = dut.ts_64.value.integer/2**16*1e-9
for k in range(10000): await ClockCycles(dut.clk, 10000)
await RisingEdge(dut.clk)
stop_time = get_sim_time('sec') stop_time = get_sim_time('sec')
stop_ts_96 = (dut.ts_96.value.integer >> 48) + ((dut.ts_96.value.integer & 0xffffffffffff)/2**16*1e-9) stop_ts_96 = (dut.ts_96.value.integer >> 48) + ((dut.ts_96.value.integer & 0xffffffffffff)/2**16*1e-9)
@@ -126,8 +125,7 @@ async def run_load_timestamps(dut):
start_ts_96 = (dut.ts_96.value.integer >> 48) + ((dut.ts_96.value.integer & 0xffffffffffff)/2**16*1e-9) start_ts_96 = (dut.ts_96.value.integer >> 48) + ((dut.ts_96.value.integer & 0xffffffffffff)/2**16*1e-9)
start_ts_64 = dut.ts_64.value.integer/2**16*1e-9 start_ts_64 = dut.ts_64.value.integer/2**16*1e-9
for k in range(2000): await ClockCycles(dut.clk, 2000)
await RisingEdge(dut.clk)
stop_time = get_sim_time('sec') stop_time = get_sim_time('sec')
stop_ts_96 = (dut.ts_96.value.integer >> 48) + ((dut.ts_96.value.integer & 0xffffffffffff)/2**16*1e-9) stop_ts_96 = (dut.ts_96.value.integer >> 48) + ((dut.ts_96.value.integer & 0xffffffffffff)/2**16*1e-9)
@@ -221,8 +219,7 @@ async def run_frequency_adjustment(dut):
start_ts_96 = (dut.ts_96.value.integer >> 48) + ((dut.ts_96.value.integer & 0xffffffffffff)/2**16*1e-9) start_ts_96 = (dut.ts_96.value.integer >> 48) + ((dut.ts_96.value.integer & 0xffffffffffff)/2**16*1e-9)
start_ts_64 = dut.ts_64.value.integer/2**16*1e-9 start_ts_64 = dut.ts_64.value.integer/2**16*1e-9
for k in range(10000): await ClockCycles(dut.clk, 10000)
await RisingEdge(dut.clk)
stop_time = get_sim_time('sec') stop_time = get_sim_time('sec')
stop_ts_96 = (dut.ts_96.value.integer >> 48) + ((dut.ts_96.value.integer & 0xffffffffffff)/2**16*1e-9) stop_ts_96 = (dut.ts_96.value.integer >> 48) + ((dut.ts_96.value.integer & 0xffffffffffff)/2**16*1e-9)
@@ -264,8 +261,7 @@ async def run_drift_adjustment(dut):
start_ts_96 = (dut.ts_96.value.integer >> 48) + ((dut.ts_96.value.integer & 0xffffffffffff)/2**16*1e-9) start_ts_96 = (dut.ts_96.value.integer >> 48) + ((dut.ts_96.value.integer & 0xffffffffffff)/2**16*1e-9)
start_ts_64 = dut.ts_64.value.integer/2**16*1e-9 start_ts_64 = dut.ts_64.value.integer/2**16*1e-9
for k in range(10000): await ClockCycles(dut.clk, 10000)
await RisingEdge(dut.clk)
stop_time = get_sim_time('sec') stop_time = get_sim_time('sec')
stop_ts_96 = (dut.ts_96.value.integer >> 48) + ((dut.ts_96.value.integer & 0xffffffffffff)/2**16*1e-9) stop_ts_96 = (dut.ts_96.value.integer >> 48) + ((dut.ts_96.value.integer & 0xffffffffffff)/2**16*1e-9)

5
tests/ptp_clock_sim_time/test_ptp_clock_sim_time.py
View File

@@ -30,7 +30,7 @@ import cocotb_test.simulator
import cocotb import cocotb
from cocotb.clock import Clock from cocotb.clock import Clock
from cocotb.triggers import RisingEdge from cocotb.triggers import RisingEdge, ClockCycles
from cocotb.utils import get_sim_time from cocotb.utils import get_sim_time
from cocotbext.eth import PtpClockSimTime from cocotbext.eth import PtpClockSimTime
@@ -66,8 +66,7 @@ async def run_test(dut):
start_ts_96 = (dut.ts_96.value.integer >> 48) + ((dut.ts_96.value.integer & 0xffffffffffff)/2**16*1e-9) start_ts_96 = (dut.ts_96.value.integer >> 48) + ((dut.ts_96.value.integer & 0xffffffffffff)/2**16*1e-9)
start_ts_64 = dut.ts_64.value.integer/2**16*1e-9 start_ts_64 = dut.ts_64.value.integer/2**16*1e-9
for k in range(10000): await ClockCycles(dut.clk, 10000)
await RisingEdge(dut.clk)
stop_time = get_sim_time('sec') stop_time = get_sim_time('sec')
stop_ts_96 = (dut.ts_96.value.integer >> 48) + ((dut.ts_96.value.integer & 0xffffffffffff)/2**16*1e-9) stop_ts_96 = (dut.ts_96.value.integer >> 48) + ((dut.ts_96.value.integer & 0xffffffffffff)/2**16*1e-9)

4
tests/rgmii/test_rgmii.py
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@@ -80,9 +80,11 @@ class TB:
self.set_enable_generator(None) self.set_enable_generator(None)
async def _run_enable(self): async def _run_enable(self):
clock_edge_event = RisingEdge(self.dut.clk)
for val in self._enable_generator: for val in self._enable_generator:
self.dut.rgmii_clk_en <= val self.dut.rgmii_clk_en <= val
await RisingEdge(self.dut.clk) await clock_edge_event
async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12, enable_gen=None, mii_sel=False): async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12, enable_gen=None, mii_sel=False):

4
tests/xgmii/test_xgmii.py
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@@ -80,9 +80,11 @@ class TB:
self.set_enable_generator(None) self.set_enable_generator(None)
async def _run_enable(self): async def _run_enable(self):
clock_edge_event = RisingEdge(self.dut.clk)
for val in self._enable_generator: for val in self._enable_generator:
self.dut.xgmii_clk_en <= val self.dut.xgmii_clk_en <= val
await RisingEdge(self.dut.clk) await clock_edge_event
async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12, enable_dic=True, async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12, enable_dic=True,