Rename byte_width to byte_lanes

This commit is contained in:
Alex Forencich
2021-04-12 15:17:02 -07:00
parent 008d903bb9
commit 3d43812c7b
2 changed files with 16 additions and 16 deletions

View File

@@ -170,14 +170,14 @@ class XgmiiSource(Reset):
self.queue_occupancy_limit_frames = -1 self.queue_occupancy_limit_frames = -1
self.width = len(self.data) self.width = len(self.data)
self.byte_width = len(self.ctrl) self.byte_lanes = len(self.ctrl)
assert self.width == self.byte_width * 8 assert self.width == self.byte_lanes * 8
self.idle_d = 0 self.idle_d = 0
self.idle_c = 0 self.idle_c = 0
for k in range(self.byte_width): for k in range(self.byte_lanes):
self.idle_d |= XgmiiCtrl.IDLE << k*8 self.idle_d |= XgmiiCtrl.IDLE << k*8
self.idle_c |= 1 << k self.idle_c |= 1 << k
@@ -271,9 +271,9 @@ class XgmiiSource(Reset):
await RisingEdge(self.clock) await RisingEdge(self.clock)
if self.enable is None or self.enable.value: if self.enable is None or self.enable.value:
if ifg_cnt + deficit_idle_cnt > self.byte_width-1 or (not self.enable_dic and ifg_cnt > 4): if ifg_cnt + deficit_idle_cnt > self.byte_lanes-1 or (not self.enable_dic and ifg_cnt > 4):
# in IFG # in IFG
ifg_cnt = ifg_cnt - self.byte_width ifg_cnt = ifg_cnt - self.byte_lanes
if ifg_cnt < 0: if ifg_cnt < 0:
if self.enable_dic: if self.enable_dic:
deficit_idle_cnt = max(deficit_idle_cnt+ifg_cnt, 0) deficit_idle_cnt = max(deficit_idle_cnt+ifg_cnt, 0)
@@ -307,7 +307,7 @@ class XgmiiSource(Reset):
else: else:
min_ifg = 0 min_ifg = 0
if self.byte_width > 4 and (ifg_cnt > min_ifg or self.force_offset_start): if self.byte_lanes > 4 and (ifg_cnt > min_ifg or self.force_offset_start):
ifg_cnt = ifg_cnt-4 ifg_cnt = ifg_cnt-4
frame.start_lane = 4 frame.start_lane = 4
frame.data = bytearray([XgmiiCtrl.IDLE]*4)+frame.data frame.data = bytearray([XgmiiCtrl.IDLE]*4)+frame.data
@@ -327,7 +327,7 @@ class XgmiiSource(Reset):
d_val = 0 d_val = 0
c_val = 0 c_val = 0
for k in range(self.byte_width): for k in range(self.byte_lanes):
if frame is not None: if frame is not None:
d = frame.data[frame_offset] d = frame.data[frame_offset]
if frame.sim_time_sfd is None and d == EthPre.SFD: if frame.sim_time_sfd is None and d == EthPre.SFD:
@@ -337,7 +337,7 @@ class XgmiiSource(Reset):
frame_offset += 1 frame_offset += 1
if frame_offset >= len(frame.data): if frame_offset >= len(frame.data):
ifg_cnt = max(self.ifg - (self.byte_width-k), 0) ifg_cnt = max(self.ifg - (self.byte_lanes-k), 0)
frame.sim_time_end = get_sim_time() frame.sim_time_end = get_sim_time()
frame.handle_tx_complete() frame.handle_tx_complete()
frame = None frame = None
@@ -380,9 +380,9 @@ class XgmiiSink(Reset):
self.queue_occupancy_frames = 0 self.queue_occupancy_frames = 0
self.width = len(self.data) self.width = len(self.data)
self.byte_width = len(self.ctrl) self.byte_lanes = len(self.ctrl)
assert self.width == self.byte_width * 8 assert self.width == self.byte_lanes * 8
self._run_cr = None self._run_cr = None
@@ -450,7 +450,7 @@ class XgmiiSink(Reset):
await RisingEdge(self.clock) await RisingEdge(self.clock)
if self.enable is None or self.enable.value: if self.enable is None or self.enable.value:
for offset in range(self.byte_width): for offset in range(self.byte_lanes):
d_val = (self.data.value.integer >> (offset*8)) & 0xff d_val = (self.data.value.integer >> (offset*8)) & 0xff
c_val = (self.ctrl.value.integer >> offset) & 1 c_val = (self.ctrl.value.integer >> offset) & 1

View File

@@ -123,7 +123,7 @@ async def run_test_alignment(dut, payload_data=None, ifg=12, enable_dic=True,
tb = TB(dut) tb = TB(dut)
byte_width = tb.source.width // 8 byte_lanes = tb.source.byte_lanes
tb.source.ifg = ifg tb.source.ifg = ifg
tb.source.enable_dic = enable_dic tb.source.enable_dic = enable_dic
@@ -164,23 +164,23 @@ async def run_test_alignment(dut, payload_data=None, ifg=12, enable_dic=True,
for test_data in test_frames: for test_data in test_frames:
if ifg == 0: if ifg == 0:
lane = 0 lane = 0
if force_offset_start and byte_width > 4: if force_offset_start and byte_lanes > 4:
lane = 4 lane = 4
start_lane_ref.append(lane) start_lane_ref.append(lane)
lane = (lane + len(test_data)+4+ifg) % byte_width lane = (lane + len(test_data)+4+ifg) % byte_lanes
if enable_dic: if enable_dic:
offset = lane % 4 offset = lane % 4
if deficit_idle_count+offset >= 4: if deficit_idle_count+offset >= 4:
offset += 4 offset += 4
lane = (lane - offset) % byte_width lane = (lane - offset) % byte_lanes
deficit_idle_count = (deficit_idle_count + offset) % 4 deficit_idle_count = (deficit_idle_count + offset) % 4
else: else:
offset = lane % 4 offset = lane % 4
if offset > 0: if offset > 0:
offset += 4 offset += 4
lane = (lane - offset) % byte_width lane = (lane - offset) % byte_lanes
tb.log.info("start_lane_ref: %s", start_lane_ref) tb.log.info("start_lane_ref: %s", start_lane_ref)