218 lines
6.3 KiB
Python
218 lines
6.3 KiB
Python
#!/usr/bin/env python
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"""
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Copyright (c) 2020 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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"""
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import itertools
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import os
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import cocotb_test.simulator
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import pytest
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import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import RisingEdge
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from cocotb.regression import TestFactory
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from cocotbext.eth import XgmiiFrame, XgmiiSource, XgmiiSink
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class TB(object):
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def __init__(self, dut):
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self.dut = dut
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cocotb.fork(Clock(dut.clk, 2, units="ns").start())
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self.source = XgmiiSource(dut, "xgmii", dut.clk, dut.rst)
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self.sink = XgmiiSink(dut, "xgmii", dut.clk, dut.rst)
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async def reset(self):
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self.dut.rst.setimmediatevalue(0)
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst <= 1
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst <= 0
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12, enable_dic=True, force_offset_start=False):
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tb = TB(dut)
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byte_width = tb.source.width // 8
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tb.source.ifg = ifg
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tb.source.enable_dic = enable_dic
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tb.source.force_offset_start = force_offset_start
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await tb.reset()
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test_frames = [payload_data(l) for l in payload_lengths()]
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for test_data in test_frames:
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test_frame = XgmiiFrame.from_payload(test_data)
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tb.source.send(test_frame)
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for test_data in test_frames:
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await tb.sink.wait()
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rx_frame = tb.sink.recv()
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assert rx_frame.get_payload() == test_data
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assert rx_frame.ctrl is None
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assert tb.sink.empty()
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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async def run_test_alignment(dut, payload_data=None, ifg=12, enable_dic=True, force_offset_start=False):
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tb = TB(dut)
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byte_width = tb.source.width // 8
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tb.source.ifg = ifg
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tb.source.enable_dic = enable_dic
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tb.source.force_offset_start = force_offset_start
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await tb.reset()
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for length in range(64, 96):
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test_frames = [payload_data(length) for k in range(10)]
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start_lane = []
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for test_data in test_frames:
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test_frame = XgmiiFrame.from_payload(test_data)
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tb.source.send(test_frame)
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for test_data in test_frames:
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await tb.sink.wait()
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rx_frame = tb.sink.recv()
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assert rx_frame.get_payload() == test_data
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assert rx_frame.ctrl is None
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start_lane.append(rx_frame.rx_start_lane)
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print(length)
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print(start_lane)
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start_lane_ref = []
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# compute expected starting lanes
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lane = 0
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deficit_idle_count = 0
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for test_data in test_frames:
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if ifg == 0:
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lane = 0
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if force_offset_start and byte_width > 4:
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lane = 4
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start_lane_ref.append(lane)
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lane = (lane + len(test_data)+ifg) % byte_width
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if enable_dic:
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offset = lane % 4
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if deficit_idle_count+offset >= 4:
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offset += 4
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lane = (lane - offset) % byte_width
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deficit_idle_count = (deficit_idle_count + offset) % 4
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else:
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offset = lane % 4
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if offset > 0:
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offset += 4
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lane = (lane - offset) % byte_width
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print(start_lane_ref)
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assert start_lane_ref == start_lane
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for k in range(10):
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await RisingEdge(dut.clk)
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assert tb.sink.empty()
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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def size_list():
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return list(range(64, 128))+[512, 1514, 9214]+[64]*10+[65]*10+[66]*10+[67]*10
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def incrementing_payload(length):
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return bytearray(itertools.islice(itertools.cycle(range(256)), length))
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if cocotb.SIM_NAME:
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factory = TestFactory(run_test)
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factory.add_option("payload_lengths", [size_list])
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factory.add_option("payload_data", [incrementing_payload])
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factory.add_option("ifg", [12, 0])
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factory.add_option("enable_dic", [True, False])
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factory.add_option("force_offset_start", [False, True])
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factory.generate_tests()
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factory = TestFactory(run_test_alignment)
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factory.add_option("payload_data", [incrementing_payload])
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factory.add_option("ifg", [12, 0])
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factory.add_option("enable_dic", [True, False])
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factory.add_option("force_offset_start", [False, True])
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factory.generate_tests()
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tests_dir = os.path.dirname(__file__)
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rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
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@pytest.mark.parametrize("data_width", [32, 64])
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def test_xgmii(request, data_width):
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dut = "test_xgmii"
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module = os.path.splitext(os.path.basename(__file__))[0]
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toplevel = dut
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verilog_sources = [
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os.path.join(tests_dir, f"{dut}.v"),
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]
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parameters = {}
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parameters['DATA_WIDTH'] = data_width
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parameters['CTRL_WIDTH'] = parameters['DATA_WIDTH'] // 8
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extra_env = {f'PARAM_{k}' : str(v) for k, v in parameters.items()}
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sim_build = os.path.join(tests_dir,
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"sim_build_"+request.node.name.replace('[', '-').replace(']', ''))
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cocotb_test.simulator.run(
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python_search=[tests_dir],
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verilog_sources=verilog_sources,
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toplevel=toplevel,
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module=module,
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parameters=parameters,
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sim_build=sim_build,
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extra_env=extra_env,
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)
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