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Cocotbext Pcie
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master
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3
master
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protected
x7
xilinx_7series
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20
v0.2.14
v0.2.12
v0.2.10
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v0.2.6
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Add sim stuff, copied from ultrascale
xilinx_7series
xilinx_7series
Add basic test
Add model
Remove dest_id from Tlp object; use completer_id instead
master x7
master x7
Remove register_number from Tlp object; use address field instead
Clean up sink pause handling
Replace task._finished with task.done()
Fix deprecated option name
Bump to dev version
Release v0.2.14
v0.2.14
v0.2.14
Handle CRS during enumeration
Check for more invalid vendor/product IDs that signify device-not-present
Minor refactor of device ID handling during enumeration
For downstream ports, only enumerate device 0
Nonzero default vendor and device IDs
Implement CRS software visibility
Rework read request splitting, add support to root complex model for splitting on every RCB
Remove extraneous instance parameters
Update S10 and P-tile models based on RX completion buffer size test results
Add PTM message types
Fix ERR_FATAL message type
Add local error reporting to US/US+ models
Update US/US+ models based on RX completion buffer size test results
Fix cfg_rcb_status
Fix link control register bits
Enforce RX completion buffer occupancy
Fix typo
Add P-Tile port number
Fix logging when using from_entity
Add Python 3.11 to regression tests
Remove recursively-expanded macros for module parameters in makefiles
Fix typo in Tlp.unpack_header()
Improve max latency timer computation based on the PCIe spec
Fix some bugs related to devices with multiple functions
Rework parameter handling in makefiles
Bump to dev version
Release v0.2.12
v0.2.12
v0.2.12
Update package versions
Pause Xilinx US/US+ sources and sinks when idle
Update package versions
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