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Created with Raphaël 2.2.08Jun27May28Nov252May3Apr24Jan28Sep15Oct30Sep1615112Add sources.listmastermasterMigrate fifo.core to CAPI2Bump versionv1.3v1.3Add backend and new core file for Xilinx FIFOE1Added some basic documentationAdd FIFO testbenchRename FIFO fwft testbench moduleAdd testbench for dual clock FIFORename fifo_reader to fifo_fwft_readerPrepare for releasev1.2.1v1.2.1Reinsert translate_off statement removed by mistakePrepare for releasev1.2v1.2Expose testbench depth_width parameterfifo_reader: Avoid using systemverilog functionChange illegal parameter values to warningsfifo_fwft: Whitespace cleanupRemove unused cnt outputUpdate .core and prepare for releasev1.1v1.1Add contraints fileSilence width mismatch warningsRefactor fifo_fwftv1.0v1.0Add dual clock fifo to fifo.coreAdd dual clock fifofifo.v: BugfixTB: Add timeout and mask writes to full FIFOUpdate FIFO and DPRAM blocks with read enableAllow writes when FIFO is fullAdd configurable read rateAdded more verbose error reportingAdded timeout in FIFO readerFix FIFO writertb: Add plusarg for setting write ratefwft: use fifo_ signals to indicate decrease of cntfifo_reader: Bug fix in read_wordInitial commitInitial commit