The precharge bit was being set at A[9] instead of A[10] meaning we were
probably never actually closing the row.  Fix to properly set A[10].

This used to come before the data was registered on the host interface.
Change so the ready is registered the same time as the data.

Signed-off-by: Stafford Horne <shorne@gmail.com>

During recent review these were annoying me

moved to dram name

These are not used.

Some people may be interested in just opening up the project in quartus.
The old sdram_controller files should go.

This makes this core play nicely when included in digi controller

In the digi recorder project we found a few problems with
the fifo and dram controller.  Also there were a few refactors
I dont remember the details be bringing them in here.

Tests work alright after this.

Also, fixup the core file

Add vlog testutils and fix some stale code.

This builds working on debugging now

WOrk on toplevel.v in progress.
This makes building and sharing a lot easier