third-party/verilog-6502
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge remote-tracking branch 'upstream/master'

Browse Source 
Change-Id: I754ba57320720ff7f46e34d80b1719a37dcd3d1e
This commit is contained in:
David Banks
2021-06-10 11:19:41 +01:00
parent fec47c5427 e6f361d764
commit 4f141c7a13
2 changed files with 7 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
README → README.md
View File

@@ -18,6 +18,8 @@ address. This allows direct connection to (Xilinx) block RAMs. When
using asynchronous memory, I suggest registering the address/control using asynchronous memory, I suggest registering the address/control
lines for glitchless output signals. lines for glitchless output signals.
[Also check out my new 65C02 project](https://github.com/Arlet/verilog-65c02)
Have fun. Have fun.
========== ==========

15
cpu.v
View File

@@ -836,15 +836,6 @@ always @(posedge clk )
* time to read the IR again before the next decode. * time to read the IR again before the next decode.
*/ */
reg RDY1 = 1;
always @(posedge clk )
RDY1 <= RDY;
always @(posedge clk )
if( ~RDY && RDY1 )
DIHOLD <= DI;
always @(posedge clk ) always @(posedge clk )
if( reset ) if( reset )
IRHOLD_valid <= 0; IRHOLD_valid <= 0;
@@ -859,7 +850,11 @@ always @(posedge clk )
assign IR = (IRQ & ~I) | NMI_edge ? 8'h00 : assign IR = (IRQ & ~I) | NMI_edge ? 8'h00 :
IRHOLD_valid ? IRHOLD : DIMUX; IRHOLD_valid ? IRHOLD : DIMUX;
assign DIMUX = ~RDY1 ? DIHOLD : DI; always @(posedge clk )
if( RDY )
DIHOLD <= DI;
assign DIMUX = ~RDY ? DIHOLD : DI;
/* /*
* Microcode state machine * Microcode state machine